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Little bit late, but maybe it could be still interesting.
Use simply Verilog-A to model this current source, it is really simple:
This code would do it:
`include "constants.vams"
`include "disciplines.vams"
module cs_exptemp(p,n);
inout p,n;
electrical p,n;
parameter real I0...
Hi,
Do you aware, that you have almost no current? have you tried increasing the current and making the same comparison?
what kind of model do you use?
You should check what is inside your transistor and how the extra devices are aligned hierarchically. Usually you have also the diodes...
What is RFC&DC-FEED?
RFC: Radio-Frequency Choke, it blocks the high frequency signals, but it acts as a short in DC and indeed it is used to feed the DC bias to an RF node.
Linear Technology does not just provide this simulation tool for everyone, but use it also for their designs, I guess that is enough as an answer ;-)
This tool has a quite good reputation, especially for SMPS design.
Actually it would be quite interesting what are the exact differences between...
run cadence scripts from shell
It you are willing to use Ocean/SKILL scripting, you can run your script fairly easily: csh("scriptname").
Basically any shell command can be used like that ...
cadence optimization
vds-vth is for sure one of the DC oppoint parameters, the name can depend on your models
Why do not you consult with the DC operating point parameters section in your models/technology documentation?
cadence source file config view post
The easiest way: Just make a symbol view for your cell (verilog-a) and include the symbol view into a schematic(testbench), if you have more views you can make a config view.
LNA for X band
X band is a frequency band, defined IEEE radar bands, it covers the frequency range between 7 and 12.5 GHz.
Do you mean you want to design an LNA with 5.5 GHz bandwidth??? (between 7 and 12.5 GHz to cover all the X band???
I do not think that it would be hard to get the models...
region of operation ... the DC operating point data can vary from transistor model to transistor model ...
the exact meaning of your numbers could be answered if you would mention which transistor model you use
coz it is not a big pleasure to do layout in ADS and Virtuoso is not a perfect tool, but if you are going through in the sufferings in the beginning, it is quite okay.
But due to my experience in the RFIC field the RFDE is the most common tool, so basically the Agilent simulation capabilities...
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