Widen width of reset signal

[brainwasher85]

Hi, anyone knows how to widen the width of a reset signal in phase/frequency detector in PLL? I tried by adding a capacitor but the value of this cap needs to be very large. Therefore I am looking for alternative way to do it.

 

[smoked]

Place even number of inverters as a delay element in the reset path of PFD. Then you'll have a long reset delay due to the propagation delays of inverters.

 

[brainwasher85]

Place even number of inverters as a delay element in the reset path of PFD. Then you'll have a long reset delay due to the propagation delays of inverters.

By adding inverters, it only delay the time of reset signal to appear. I need to increase the width of the reset signal itself. I attached a picture to explain more.

 

[smoked]

if you are considering to increase the minimum pulse width of the PFD you can still use additional inverter delays, therefor you can avoid dead-zone non-ideality by increasing the reset path delay. what I was mentioning is about minimum pulse width.

 

[drabos]

current starved inverters