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Recent content by dinesh hegde

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    Help with virtuoso "Routing" function

    Yes, You can use this to try different routing possiblities. First create a black box of your layout with pins, area and devices placed. You have to create one control file which includes the details like min routing width, min routing space etc. You need to provide this file in "Use Rules...
  2. D

    what is headroom voltage.

    fullscale voltage minus voltage measured at a node within network which is referred to fullscale voltage is the headroom voltage.
  3. D

    How to avoid latchup error?

    PMOS and NMOS should be isolated to avoid latch up. Surround the NMOS with NWELL ring and surround the PMOS with P+ ring. ( you can use deep nwell also to isolate if your process supports that)
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    How to draw the layout of diode

    If common substrate is P- then, 1. Put a N-WELL 2. Place two rectangles of active (diffusion layer) side by side. (The area of the recangle should be equal to area of diode). 3. Then cover one of the active with TAP layer to invert the diffusion type. 4. Place diffusion contacts on both the...
  5. D

    power/ground which net is more clean?

    Both are not good, but I think ground is beeter than power.
  6. D

    Charges accumulated during Antenna Effect

    Whether wafer is grounded during wafer processing steps?
  7. D

    metal connect, which better

    From Electromigration point case A is better.
  8. D

    Have a question about Space

    With minimum space coupling cap is more between them. -Dinesh
  9. D

    How to design pad ring for Two stage opamp

    Also you need to plan below things, 1. How many power/ground pads you have? 2. How many signal pads you have? 3. Do you have any pads only for testing purpose? 4. What type of package ? -Dinesh
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    Charges accumulated during Antenna Effect

    Thanks, We usually add a Antenna diode to discharge the charges. If both type of charges gets accumulated then how the diode operation will be? My assumptions, (diode is placed on p-substrate) Case1 : Metal is charged with negative ions then, diode is forward biased and it will discharge the...
  11. D

    unbound pin in assura LVS

    Please check if proper layers are used for putting pins. We have faced these issues if pins layers are improper.
  12. D

    Charges accumulated during Antenna Effect

    What type of charges (positive or negative) results in Antenna violations ? I guess its both, but I need confirmation in actual process.
  13. D

    What are the types of shielding available?

    I think there wont be any problem if one side VDD and other side VSS until you do not make a loop in it. But I want to understand what is the requirement that you are choosing such option. -Dinesh
  14. D

    Effect of W < L for a MOSFET in layout and later stages

    I do not know if there any problems realted to fabrication. But if we think of analog application where mismatch is critical thing then, yes "Mismatch is less if W/L ratio is less" You can refer to paper "Optimizing MOS Transistor Mismatch" by Simon J. Lovett, Marco Welten, Alan Mathewson, and...
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    What are the types of shielding available?

    Following may help you, 1. If Signal in Met1, bottom plate --> Poly top plate --> Met2 Either side --> Contact and Via Connect all plates to either POWER /GROUND depending on situation. 2. If signal in METx bottom plate --> Met (x-1) top plate --> Met(x+1) Either side --> Via(x-1) and Viax...

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