Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
hi shobhit,
thanx for reply, i have tried these steps and also took help from attribute user guide but still getting the assigns in netlist.
Is there any setting that disables the removal of assign statements.
thanx
hello folks,
There are three types of wire load models, which one is selected for the perticular synthesis and its selection is depends on what parameters??
kindly help me.
Regards
Dha_synth
hello all,
there are number of assign statemnts are there in the netlist i have generated using RC,
can anybody please tell me how to add buffer or inverter to avoid the consequences in the netlist.
Any other technique to resolve the problem will be welcome.
thanx in advance
dha_synth
hello all,
In RTL compiler while synthesis, at the time of elaboration tool optimize mux and the datapath.
Can anyone please explain in detail.
Thanx in edvance
dha_synth
Dear dpaul,
i do not have any problem in running this process, i was trying to figure out the case of elaboration without using lib. and i know the importance of lib in the synthesis very well
i am trying to run these commands one by one .
i just want to know the relation of elaboration step...
Error : Failed to execute command. [LBR-116] [elaborate]
: No target technology library was loaded.
: Set the root 'library' attribute to a (list of) library name(s).
and i am using this commands, previously i have included search path for library and hdl...
hello dpaul,
thanx for the reply
I got ur point of of including .lib for macros but, i have tried to elaborate a simple full adder which do not contain any macro or other things. The rc still shows the error of not including any library.
As written by you,
during elaboration,RTL Compiler...
Re: RTL Compiler, elaboration command
thanx dpaul for the answer,
as far as i am concirned after elaboration tool only informs about the usable logics and the usable sequential logics of the li-cells.
I am not getting what kind of permitted details you are talking about.
hello all,
This might be a silly question but it really made my concepts struggling.
We know conversion from rtl to gate level netlist or mapping of the rtl logic with library cells are done at the synthesis time but, we also cannot perform elaboration of the design reading library file...
Thanks for the reply.
In your forst reply you mentioned " Depending on the stage of the ASIC flow, you have to choose the relevant library"..
I didnt get meaning of this line.
thanks for reply,
How do you exactly relating PVT to stages of asic flow?
and why slow cold libraries are usually prefer?
Do we consider the availability of the components in the libraries for synthesis?
Thanks
hello all,
what are the parameters needs to be consider while choosing a specific library file for any synthesis process? or what all conditions that can vary from library to library
Thanx in advance
dha_synth
hi folks,
I am working on the rtl compiler for 2 months but didt realise the actual difference between generate sdc file in rtl compiler and hand written sdc file which is used for the synthesis.
please differenctiate.
Thanks in advance
dha_synth
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
