assign statement in rtl compiler

[dha_synth]

hello all,

there are number of assign statemnts are there in the netlist i have generated using RC,
can anybody please tell me how to add buffer or inverter to avoid the consequences in the netlist.

Any other technique to resolve the problem will be welcome.

thanx in advance
dha_synth

 

[shobhit]

1) Set the following root attribute to TRUE
attribute ==> remove_assigns
2) instruct RTL compiler which buffer to use , using the blow command
set_remove_assign_options -buffer_or_inverter <BUFFER LIBCELL NAME>
3) run incremental optimization.
synth -to_mapped -incr

--
Shobhit

 

[dha_synth]

hi shobhit,

thanx for reply, i have tried these steps and also took help from attribute user guide but still getting the assigns in netlist.
Is there any setting that disables the removal of assign statements.

thanx

 

[dpaul]

Your answer might be in the following EDA Board threads!

https://www.edaboard.com/threads/85322/
https://www.edaboard.com/threads/31508/
https://www.edaboard.com/threads/164140/

 

[cyrax747]

Hi

Why in specific we check for assign statement ?? Why it shudn't be present in the netlist ?

 

[rca]

Well now the cadence (14.2) flow is able to handle with the assign inside the netlist.