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Recent content by dendrite

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    pipelined adc problem,ergent!

    Use Verilog-A simulation to determine the causal link between the stages2 and stage3.
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    Comparator architecture that will achieve 1.6mV resolution

    comparator design use dynamic comparator
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    Different between macros

    The deference of LEF. Maybe you'd read the manual of CADENCE.
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    Looking for tools and tutorials for Cadence

    Re: cadence---help me you can get it in this forum!
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    What is the coner simulation and how it works?

    Re: coner simulation If you have the lib set of hspice! you can do simulation.
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    Introduction To Probability And Stochastic Processes (Book)

    Probability, Random Variables and Stochastic Processes 3rd This is the 3rd edition of the book. (the only version that I have found) ISBN 0-07-048477-5 1991 the better one. you can download it form this forum! Please search it.
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    What are the hot keys in Cadence?

    Cadance Hot Keys Please . show instances , show the layout
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    I want to buy this kind of CMOS OP amp.

    Would you buy OPAMP macro IP?
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    Detailed design flow of PLL

    flow pll best reference h**p://www.fujitsu.com/downloads/MICRO/fma/pdf/PLLapp.pdf
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    Designing a 200MHz CMOS oscillator with crystal base IC

    200MHz CMOS Oscillator PLL is the best choose. h**p://www.fujitsu.com/us/services/edevices/microelectronics/asic/mixedsignal/
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    Looking for detailed topology of pipeline ADC 8bits circuit

    pipeline ADC circuit Form the Prof. Gray's homepage, you can get something useful. h**p://kabuki.eecs.berkeley.edu/ Good luck!
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    about ALL Digital Delay Line

    Thank you. I'll do it.
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    About analog IP design

    Try this one. Springer - A Platform-Centric Approach to System-on-Chip (SOC) Design
  14. D

    Different results in Hspice and Spectre

    Re: hspice vs spectre If you use the large mixed signal circuit. you'll feel the speed. The third choice is ultrasim. Maybe it's the best.

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