Different between macros

[vsrpkumar]

What is the difference between soft macros and hard macros.Can any one give examples for this .Thanking you
VSRPKUMAR

 

[joe2moon]

Soft Macro:
- RTL source code in Verilog/VHDL which can be synthesized into different technology libraries.
- Example: ARM7TDMI source code

- Can be targeted into user-defined process technology, such as TSMC 0.18um or UMC 0.13um, ....

- Provided in VHDL(.vhd) or Verilog(.v) format
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Hard Macro:
- GDSII database in specific process library.
- Example: PLL, Memory, or TSMC 0.13um ARM7TDMI hard core.
( https://www.arm.com/products/CPUs/ARM7TDMI.html)

- Fixed size/shape/technology
- Usually provided with other views for simulation/synthesis/..., such as
.v, .lib, .lef, ....
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[dendrite]

The deference of LEF. Maybe you'd read the manual of CADENCE.