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Recent content by conmourtz

  1. C

    vhdl to verilog code convert

    Hello there. Could anyone help me with translate this vhdl code to veriolog code? Thanks in advance. it is about 3 state machines. i know how to convert one state machine from vhdl to verilog but with 3 i cannot figure out what the states will be. type tx_sequence is (high_setup, high_hold...
  2. C

    How to divide with SIC sbn instruction

    Hello there, I want to implement the C code c = a div b; on SIC with sbn instruction. Any help with this? The command does the following: sbn a,b,c # Mem[a] = Mem[a] – Mem[b];if (Mem[a]<0) go to c I am looking forward to hearing from you and i would appreciate any kind of help. thank...
  3. C

    pad insertion netlist for soc encounter

    i don't have any problem for filler cells of standar cells on core area. My problem is on pad fillers. I checked my library and lef files for the pads and it gives me several pads for fillers. i use them from the biggest to the smallest one and i still have some gaps which their margin is...
  4. C

    pad insertion netlist for soc encounter

    one more thing, when i import the netlist on soc encounter with the pads and i change the utilization of the design i have to fill the gaps between 2 pads with filler pads right? when i do that, i reach on a point that i don't have any smaller pad to fill the gap. what am i supposed to do after...
  5. C

    pad insertion netlist for soc encounter

    and what about drive and loads? are they needed or not when i import the pads on the rtl netlist?
  6. C

    pad insertion netlist for soc encounter

    Hello there. I have a problem with the pads netlist for soc encounter. I want to connect them propper (input pads on A and output pads on Y side which is on the core area of my design). Could anyone correct my netlist so the pads connect with the core area design propperly? Thank you.
  7. C

    Sroute on pads/nano route problem on soc encounter

    if i don't include these power wires on the Power -> Connect Global Nets option on Soc encounter when i check the power it shows me warning for these pads that are not connected. So, i connect them all with globalNetConnect vdd! -type pgpin -pin vdd! -inst * -verbose globalNetConnect gnd...
  8. C

    Sroute on pads/nano route problem on soc encounter

    the ring over pads which is on metal 3 is when i special route the design. i select all the power nets (5 of pads + 2 of core) and the tool automatically connects the power ring over the pads. What can i do for that? To avoid these short violations for the power ring on pads?
  9. C

    Sroute on pads/nano route problem on soc encounter

    I changed the RTL on my design. Now pads are correctly connected (as far as i can see on encounter and no warnings/errors on DC). The power wires are all connected on pads, but they have still the short violation problem. Also some wires from pads (as you can see on my initial post attachments)...
  10. C

    short violation in soc encounter

    I have the same problem too. Power nets on pads have short violations. Also, some wires from pads that lead to a macro cell on my design have short violations. what could be wrong?
  11. C

    Sroute on pads/nano route problem on soc encounter

    i don't have an area specification for my design. You mean that i have to make a new toplevel on my design to connect the pads with the main design. Could you upload an example? I attach the top level that i made and the warnings from dc Do you see something wrong or how i can correct my...
  12. C

    Sroute on pads/nano route problem on soc encounter

    i insert the pads on my design by modifying the netlist that design compiler exports. after that when i import the design on encounter i have to connect the power ring/stripes. the power pads connected with 5 power wires and the core design with 2 others. when i do the special route i choose all...
  13. C

    Sroute on pads/nano route problem on soc encounter

    Hi there, I have a design on Soc encounter. As you can see on the following attached files i have problem with pad vdd/vss power wiring on special route. i do the special route (i have 5 power signals for pads and 2 for core area). The 5th power siganl is only connected on the top of the...
  14. C

    usage of ldd command on edatools

    Hello there i wonder which is the usage of ldd command on several edatools such as cadence soc encounter, synopsys design compiler and more... (i guess it has to do with the requirement libraries which these tools needs to run) Please tell me how to execute the command and if my guess was...
  15. C

    stream in the gds file to cadence virtuoso

    new problem appeared on import stream on virtuoso: WARNING (36): Stream layer-datatype '34:10' is not defined in the layer map file. All the objects on this layer-datatype will be ignored. i have 304 of them on logfile..any suggestions/help of what could be wrong? ty
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