pad insertion netlist for soc encounter

[conmourtz]

Hello there. I have a problem with the pads netlist for soc encounter. I want to connect them propper (input pads on A and output pads on Y side which is on the core area of my design). Could anyone correct my netlist so the pads connect with the core area design propperly? Thank you.

 

[rca]

Why you don't instantiate the pad at rtll level ?
By this you guaranties with yours tests the correct connections and behavior.

 

[conmourtz]

and what about drive and loads? are they needed or not when i import the pads on the rtl netlist?

 

[rca]

Drive and load is to modeling the PCB board.

 

[conmourtz]

one more thing, when i import the netlist on soc encounter with the pads and i change the utilization of the design i have to fill the gaps between 2 pads with filler pads right? when i do that, i reach on a point that i don't have any smaller pad to fill the gap. what am i supposed to do after? can i leave this small gap with no filler or can i do something else to fill it?

Basicall i tried the command

addIoFiller -cell PERI_SPACER -prefix IOFILLER -fillAnyGap

and it overlaps some fillers and fillers with pads that it uses to fill the smaller gaps so i have violations there...

i am looking forward to hearing from you and thanks for your till now help

best regards.

 

[rca]

Normaly the pad library should provide a filler for the smallest grid possible in the relatede technology.
Same idea for the std cell filler.

 

[conmourtz]

i don't have any problem for filler cells of standar cells on core area. My problem is on pad fillers. I checked my library and lef files for the pads and it gives me several pads for fillers. i use them from the biggest to the smallest one and i still have some gaps which their margin is smaller than the smallest filler pad that the library contains.

 

[rca]

The filler pad could be overlap together?

 

[a_mythpi]

Hi,

No. As far as I know the filler cells cannot overlap each other. Try this:

1. Prepare a rough floor plan by giving only the cell utilisation and the ratio

2. Check the total width of the floorplan. By total width I mean including the IO pads

3. Now readjust the Length or width according to the smallest filler cell available ( In my case it was 0.2 micro met). Specify the floorplan by adjusting the die size now and make it an integral multiple of the smallest filler cell.

this should work. It sure as hell did for me!

 

[chagul]

In this training we will start with a structural verilog design netlist (from synthesis) and create step by
step a physical layout that can be manufactured. To keep runtimes reasonably low, we will use an
example design with a (slightly) lower complexity than most student design projects. ValidationProtocol