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Recent content by cnu4u

  1. C

    Guidance needed in understanding Logical DRCs

    Thank you wesleytaylor. I want to know about Max.transition, Max. Capacitance and Max. Fanout DRCs. What will happen to the design if these are not met?
  2. C

    Guidance needed in understanding Logical DRCs

    Hi all, Please let me know why LOGICAL DRCs are to be met?What are effects if the design doesn't meet logical DRCs?Can we tape-out even if we have logical DRC violations in the design? Thanks in advance.
  3. C

    Coupling Capacitance

    Sorry if I didn't mention clearly. Consider a transmitter and a receiver connected by a bus. So there is a possibility of two way communication between them, like acknowledge signal or any such kind of communication. I'm asking about such scenario.
  4. C

    Coupling Capacitance

    Can we reduce coupling Capacitance effect in a bus structure by placing two nets adjacently which are driven in opposite directions?
  5. C

    CMOS transistor width length ratio calculation

    @zulqar..I've attached the screenshot of the schematic which implements AB+C logic.Kindly please help me with this.Thanks.
  6. C

    CMOS transistor width length ratio calculation

    @gs65..Pull up and pull down networks should have same drive strength.Switching threshold should be vdd/2.
  7. C

    CMOS transistor width length ratio calculation

    How to calculate (W/L) of pull up and pull down networks.Please help me with detailed description or provide me with some material. Thanks.
  8. C

    Doubt in Verilog using always and forever

    Thank you Dave.
  9. C

    Doubt in Verilog using always and forever

    What is the difference in generating clock using 'always' and 'forever'? Please gimme detailed answer. Thanks in advance
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