Guidance needed in understanding Logical DRCs

[cnu4u]

Hi all,
Please let me know why LOGICAL DRCs are to be met?What are effects if the design doesn't meet logical DRCs?Can we tape-out even if we have logical DRC violations in the design?
Thanks in advance.

 

[wtr]

Hi all,
Please let me know why LOGICAL DRCs are to be met?What are effects if the design doesn't meet logical DRCs?Can we tape-out even if we have logical DRC violations in the design?
Thanks in advance.

Can you give me an example of anything in particular?

For example you could be getting DRC errors about not having correct tristate buffers because in your code your vhdl use inout for signals & the synthesiser will optimise out the unused aspects.

These types of DRC's don't even need to be met. It's all dependant on what you're trying to achieve.

 

[cnu4u]

Thank you wesleytaylor.
I want to know about Max.transition, Max. Capacitance and Max. Fanout DRCs. What will happen to the design if these are not met?