CMOS transistor width length ratio calculation

[cnu4u]

How to calculate (W/L) of pull up and pull down networks.Please help me with detailed description or provide me with some material. Thanks.

 

[gs65]

What information is given .

 

[cnu4u]

@gs65..Pull up and pull down networks should have same drive strength.Switching threshold should be vdd/2.

 

[IntuitiveAnalog]

For the calculation of W/L of PUN or PDN , first of all you have to take a worst case path (say in PDN ) , then the equivalent W/L of this path has to be equal to that of NMOS in an inverter.
If you find difficulty in finding the worst case path , post the schematic of your PUN or PDN , then only actual calculation of W/L can be done.

 

[cnu4u]

@zulqar..I've attached the screenshot of the schematic which implements AB+C logic.Kindly please help me with this.Thanks.

 

[IntuitiveAnalog]

If we take PDN then Q2 and Q3 will be in worst case path , their W/L should be 2n where n=(W/L) of nmos in inverter .And W/L of Q4 should be equal to n .Depending upon your L you can find W . Similarly you can find aspect ratio of PUN txors .
The attached file will be helpful to you .

 

[dick_freebird]

What do you want from these "networks"? That's where to start.

A digital guy may just want a roughly right answer, corner to
corner. An analog guy might be on the hook for PSRR and
then L gives you the deflection per supply movement, and W
is what it has to be to get the number.

Formula would be a starting point at best.