Doubt in Verilog using always and forever

[cnu4u]

What is the difference in generating clock using 'always' and 'forever'? Please gimme detailed answer. Thanks in advance

 

[dave_59]

For most simulation usage, there is no functional difference between

always 
  begin 
    #10 clk = 1; #5 clk = 0;
  end

and

initial forever
  begin 
    #10 clk = 1; #5 clk = 0;
  end

Semantically, the two forms are different even though they have the same end result.

An always construct declares a permanent thread of execution. At time 0, it starts the thread by executing the procedural statement that is part of the construct (in this case the begin/end block). When the procedural statement finishes, it executes it again. This thread of execution exists for the entire simulation and can never be terminated.

An initial construct declares a thread of execution that exists as long as there are procedural statements to execute. At time 0, it starts the thread by executing the procedural statement that is part of the construct (in this case the forever statement). When the procedural statement finishes, the thread terminates. In this case the thread does not terminated because the looping statement never ends.

More specifically, there are a few more things you can do with a forever statement that you cannot easily do with an always construct. By adding a delay before executing the forever statement you can introduce a phase shift.

initial #2 forever
  begin 
    #10 clk2 = 1; #5 clk2 = 0;
  end

clk and clk2 will have the same period, but clk2 is shifted by 2 timeunits.

As a looping statement, you can break out of a forever loop, and if you name the statement, you can disable it. So you can terminate the process created by an initial block. There is no way to terminate the process created by an always block.

 

[cnu4u]

Thank you Dave.