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Recent content by Clunixchit

  1. C

    Help me with M1/M2 spacing in the place and route stage

    M1/M2 spacing ? Hello there, In the place and route stage, I have to fill in the metal 1 spacing and metal 2 spacing. However I don't know how to deduce these values. I'm looking at its LEF file, but don't know at what I should be looking for. Can anyone please shed some light please ?
  2. C

    What are the pros and cons of using dual or quad ADC ?

    dual or quad ADC ? Hello there, I have 4 analog outputs (2 * IQ) from a dual IQ demodulator. These signals are filtered and fed to a quad 12bits ADC. The output of the ADC should be through SPI communication to a Microcontroller. My question is what are the pros and cons of using : - a quad...
  3. C

    product engineer interview questions

    Hello, What are the interview questions that a candidate will have for a product engineering position ? thank you.
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    Latch is inferred due to RTL coding

    will anyone agree with me if I take inferred latch as example to justify: One shouldn't jump into conclusion just by looking at the combinational area, to judge the quality of a design. If take no_mad's example, there is a high probability that in the case of - without default -...
  5. C

    porting define_design_lib to RTL compiler

    define_design_lib Hello there, I've been using Synopsys DC for a long time. Now, it seems that due to a financial issue, I'll be forced to opt RTL compiler. Since the last 2 days, I've being porting my synthesis scripts for trials. However, I've been unable to figure out the replacement of...
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    CAD Interview questions

    cad interview questions Hello there, I 've seen this in forum many interview questions in respect to VLSI design. However I'm curious to hear some VLSI CAD interview questions. Can you share some ?
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    From VHDL/Verilog to layout

    Yes, you can. Have a look at the cheapest way via Fedora Electronic Lab. **broken link removed**
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    missing presto_vhdl.prims

    presto_vhdl.prims Hello there, I'm trying to use ACS for the first time and during the analysing process, DC spits Error: Can't open Synopsys primitive package '/home/apps/synopsys/synopsys.2007.12-SP4/auxx/syn/presto_vhdl.prims' (HDL-1) that file is actually missing in the install...
  9. C

    estimation of gate count

    1. Count the number of (hier) instances on the design 2. Multiply that number in accordance to their respective gate count (see its attributes)
  10. C

    Fixing Setup & Hold Violations

    how to fix setup time violation Can one identify those cells either : * inserted by insert_buffer command, or * auto buffer insertion by DC during optimizations ? Perhaps there is a special attribute on those cells ?
  11. C

    schematic generation with design vision

    Would you mind give me some details in order to guide me through my baby steps with design vision. please ?
  12. C

    combi and non combi cells

    I mean: if number of non-combinational cells decreases from one DC version to another, this would mean that my design is poorly written. if the number of combinational cells varies from one DC version to another, this would implicate that the new DC version has better algorithms. Are there...
  13. C

    combi and non combi cells

    Hello there, I'm just curious how is combinational and non combinational gate counts interesting in report_area (from Design Compiler) ?
  14. C

    schematic generation with design vision

    Hello there, I wonder if it's possible to automatically generate the schematic via design vision (if all the libraries are passed) if I parse a startpoint and an endpoint. My idea is to have a schematic of: report_timing -from X -to Y for a powerpoint presentation. I wish to do that via a...
  15. C

    Synopsys DC A-2007.12 name rules

    Hello, I use in my internal scripts the design names (the last column) from report_area -hierarchy. However with the versions A-2007.12-SP2 and A-2007.12-SP3 their naming rules have changed. Hence my scripts are broken. Example: DC versions below A-2007.12-SP2 : a particular design name is...
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