combi and non combi cells

[Clunixchit]

Hello there,

I'm just curious how is combinational and non combinational gate counts interesting in report_area (from Design Compiler) ?

 

[gliss]

It depends on your design and goals, right? Do you want more combinatorial gates. Combinatorial and complex gates have a certain impact on area and timing.

 

[Clunixchit]

I mean:

if number of non-combinational cells decreases from one DC version to another, this would mean that my design is poorly written.

if the number of combinational cells varies from one DC version to another, this would implicate that the new DC version has better algorithms.

Are there any such reasons which indicate how good my design is written or how good DC algorithms are ?

 

[gliss]

I mean:

if number of non-combinational cells decreases from one DC version to another, this would mean that my design is poorly written.

Not necessarily. It just means one version has a different synthesis engine. Look at the reports to see which one was more efficient for your design. For example, instead of bunches of primitive logic cells like NAND, OR and NOT, the synthesis engine might choose to combine logic and instantiate complex AOI cells.

if the number of combinational cells varies from one DC version to another, this would implicate that the new DC version has better algorithms.

Quite possibly, but not necessarily true. Look through the Synthesis reports and Primetime reports to see which synthesis engine is better optimized for your design.

Are there any such reasons which indicate how good my design is written or how good DC algorithms are ?

There shouldn't be a complex relationship between your RTL code and the generated netlist. Good RTL should produce a good netlist and a bad code tends to create an inefficient implementation. You might want to take specific code from your design and look at the Design Compiler manual for insight on how the engine might transform your RTL.
You might also want to check your synthesis constraints.