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Recent content by climber73

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    Layout RF - request for resources

    Re: Layout RF Isn't easy to summarize the line guide for RF layout. - symmetry - minimize capacitance parassitcs in critical net - take in account the coupling due to high frequency - isolate and protect sensitive/aggressive blocks - good contact of substrate Anyway a good reference is "The...
  2. C

    Need way to find resistance of path via verificaton

    Re: resistance of path I don't think you can verify it by some tool. Only way is calculate it manually considering width, lenght and resistivity and don't forget to take in account the VIAS. Bye Bye
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    Separate grounds for Analog and Digital blocks

    digital block guardring In calibre, you can select CONNECT NET BY NAME from LVS OPTION. Bye bye
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    Why dummy metals dont require OPC?

    Re: OPC for dummy OPC is a photolithography enhancement technique commonly used to compensate immage errors. OPC increase the fidelity of pattern transfer to the wafer. Usually in technology used by me, you have the possibility to generate dummy with or without OPC.
  5. C

    ASSURA VS CALIBRE VS DIVA

    THE WINNER IS ....... CALIBREEEEEEEEEEE Bye Bye
  6. C

    Matching of capacitors in a DAC

    hello, why you don't use the 2fF or 4fF as unit capa? In this case you can use 2 capa to obtain 1fF, but you can reduce the number of capa and so you can have more simple routing. Bye
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    someone have info about the TSMC 0.13 PDK?

    TSMC 0.13 PDk info Hello, someone have info about the TSMC 0.13 PDK? MIM available? How much fF/u ? ULL mos, are available? thanks Bye
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    What are these error from LVS: psub_StampErrorMult

    triple well device lvs The triple well could be solve the problem but, can you use it? You should discus this with the designer. In your layout you have Psub contact connected in different point. you can solve this error in two way: 1) find the floating contact, and connect them all togheter...
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    How to layout the pads? Questions and Answers

    gndpad Hello, in your "Design Rule Manual" or "Assembly Rule Manual" you should find all the info about the PAD. Usually different PAD structure are are used for different use, es: RF signal PAD, Power supply PAD, Wire bonding, Bumping ....... Bye
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    Common Centroid & Interdigitization

    layout common centroid current mirror In my opinion the common centroid is the best choice in terms of matching, but of course in High Frequency is all more difficult. You have to choice the best compromise between matching-simmetry-parassitics. Good luck
  11. C

    some questions on layout?

    1) Yes, the ground plate and the power plate should be big enough to decrease the impedence. The capacitance between the POWER and GROUND is welcome. 2) Of course, you should take care about the routing of the signal path. You have to avoid to cross noise signal, power or gorund. Bye
  12. C

    What needs to be taken care of in layout when doing layout of Charge Pump PLL?

    pll sg Take about the position of your Charge-Pump Vs other sensitive block like VCO, divider and other. Bye
  13. C

    I want to know importance of floor plan...

    A good layout start with a good floorplan. The advantage of floorplan are more and more: - Estimate and optimize the area. - Understand the correct position of each block in order to avoid to put noise block near sensitive block. - indivuate the critical path. - understand how you can separate...
  14. C

    How to decide the power bus width?

    Re: power bus width For power and gnd don't use minimum width in according with electromigration rules. Bye

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