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Recent content by chip-monk

  1. C

    SDF Errors: ncelab: *W,SDFGENNF

    When I try to do an sdf annotation in Cadence I get lots of warnings like: ncelab: *W,SDFGENNF: Generic "TPD_ip1_op_posedge" not found in component "test.dff_1.g16:" <./gen_test1.sdf, line 20>. The generic "TPD_ip1_op" is present in the library vhdl model file but the _posedge generic is not...
  2. C

    Compiling Verilog and VHDL files together in Cadence

    Hi, The synthesized netlist from Cadence RTL Compiler is in Verilog whereas the library cell definitions (used for gate level simulations) are in VHDL. Can cadence use both VHDL and Verilog files together? Thanks.
  3. C

    Cadence: Steps for Functional verification of synthesized netlist

    Hi, Thanks for the quick reply. I am using VT Standard Cell Library and there is no *.v file containing all the gates such as and, inv etc used in the synthesized netlist. So, how do I point to the library gates when I have the synthesized netlist, sdf, and *.lib file but no verilog file with...
  4. C

    Cadence: Steps for Functional verification of synthesized netlist

    How does one functionally verify a netlist synthesized using the RTL Compiler? Please give steps and associated commands. Thanks.
  5. C

    set_max_delay for ports inside the design

    Could you help with the error?
  6. C

    set_max_delay for ports inside the design

    Below is the Verilog code I am trying to synthesize. I wish to set some max delay constraints on the adders inside this design. when I try to use the following command for constraining a path of a 16 bit adder (adder_ks16) in the design: set_max_delay 4 -from {regAcc[0]} -to {sum16[0]} the...
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    The combinational loop has been disabled.

    Following is a segment of a Verilog code I'm trying to synthesize. adder_ks16 ks16_2(c_out, ,notoutAcc,SADmin,1'b0); always @(posedge c_out or posedge signal_m) begin if(signal_m == 1) SADmin <= 16'b1111_1111_1111_1111; else...
  8. C

    Setting Constraints and Performing Timing Analysis Using Encounter RTL Compiler

    Does anyone have the following manual? 'Setting Constraints and Performing Timing Analysis Using Encounter RTL Compiler' If so please provide it here. Thanks.
  9. C

    Problem running cdb2oa

    Hi, I am trying to use the Standard Cell Libraries provided by Virginia Tech for PnR, which require the NCSU kit. I am using the NCSU 1.6 beta version which works with the Cadence IC 1.6 version, however the VT Cell Libraries have been designed for the older version and have to be converted...
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