Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hello,
I'm facing an issue using Canalyzer 7.6.68 (SP3)
I want to insert a program node to do some elaborations when the bus is running, but the item of the right-botton mouse menu is disabled.
If I disconnect the cancase, close and restart the program, then the item is enabled.
This...
hi,
I'm looking for a Wifi dongle (no a module) to use with my micro LPC313x (arm based) and linux (kernel 2.6.33).
Do you have experience on this job? Can you suggest me how to procede and what is the best dongle available to use with arm/LPC313x?
Thank you in advance.
Hi
I would like to ask you which is the best toolchain to develop, simulate, cross-compile and testing (both user application and kernel), starting from the choise of the most suitable host operating system.
At the moment I'm working with an pc with Ubuntu, codeblocks and the eldk42. I have a...
Hello,
I'm planning to develop an application on ARM9 with Linux embedded.
This is the first time and I'm looking for both debuggers and IDEs suitable to do the job.
I've been using now the KEIL uVision4 with the ULINK, but I don't know if I can use it with Linux.
I'm evaluating other products...
Hello,
I'm planning to purchase a new emulator for my TI DSP C6748 (XDS100 was very inefficient).
I've seen two solutions: the Spectrum Digital XDS510 and the Signum JTAGjet-CCS (cheaper).
Does anyone have experience with these two emulators and can tell me if the JTAGjet is good?
Thanks!
sei was right, CCS is the only TI IDE, based on Eclipse and, then, Java. I think it isn't so much easy for beginners: a lot of configuration feactures (too much and sometimes redundant), slow and some small bugs.
Often it stalls due to Java/eclipse and, if you use the low-cost jtag emulator...
Hello,
Some weeks ago I posted my problems concering CCS and XDS100v2 jtag emulator (without responce, unfortunatelly).
Now, I'm looking for a better jtag emulator and debugger to use with the TI C6000 family, and possibly with NXP LPC3130.
Spectum Digital XDS510 is the TI solution, but...
Hello,
I would like to share my CCS experience, and problems, in using CCS.
I'm working with a LOGICPD board for evaluating a C6748 Texas Instrument DSP (this is my first time with DSP and I have experience with 8bit micro programming).
I suddenly found CCS a rich, but heavy, enviroment and...
Hello,
I need to load a bmp picture in the DDR of my DSP, but I'm new in using DSP and with this type of application.
I would like to use only C language.
Can anyone help me, with some examples? Thanks.
Hello everybody,
This is the first time I work on DPS and I'm working now with a Texas Instrument DSP C6748 (the development kit is the LOGIC OMAP-L138 EVM).
I came from the 8-bit microcontrollers' world and I'm a bit stuck in using the code composer studio. I had several problem with jtag...
do file modelsim
Hi,
of course, you can have the unisim library no compiled.
Run the comand 'compxlib -h' at the modelsim prompt. It's easy to compile.
For the second question, I don't know. Usually I took that error when I was simulated a sinthesied design through a testbench file which...
Re: Xilinx or Altera?
I have the same problem:
I've to create a design in simulink, but using Altera DSP builder or Xilinx System generator. I don't know which board I'll use.
what is the best toolbox?
And then I've to translate simulink model on vhdl. It's possible? I'll obtain a good vhdl...
fractional value
Hi, this is my problem (it's the continue of the topic:"frequency divider with NCO"):
I've to describe a clock frequency divider by a fractional value. All digital in VHDL (also behavioral). What can I do ?
Thanks for your advices
Charlie
VHDL, Verilog
Hi.
:arrow: What is the difference between VHDL 87 and VHDL 93?
:arrow: I'd like to learn the Verilog language. Someone can suggest me how to start and the advantages with respect VHDL?
Thanks
Yes. I've used an inappropriate sentence.
I've to generate a block for the code rate of a PRN sequence (CDMA demodulation for GPS channel receiver). Up to now, I known the frequency of the code and it was created by coreclk freq division (with NCO). But I didn't know the core frequency! This was...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.