What's the difference between VHDL 87, 93 and Verilog?

[Charlie.za]

VHDL, Verilog

Hi.
:arrow: What is the difference between VHDL 87 and VHDL 93?
:arrow: I'd like to learn the Verilog language. Someone can suggest me how to start and the advantages with respect VHDL?

Thanks

 

[zanov]

Re: VHDL, Verilog

Hi.
:arrow: What is the difference between VHDL 87 and VHDL 93?
:arrow: I'd like to learn the Verilog language. Someone can suggest me how to start and the advantages with respect VHDL?

Thanks

Simply 97 has some new operators as xnor, also a variable can be shared and declared outside of the process or many processes can have access to this shared variable,notion of group was intriduced in 97, new attribute "foreign", ascending,image,value are now in vhdl97.

VHDL and Verilog do the same thing. The advantage is mostly in Verilog in C-lookalike.
try tutorials for verilog for now:

 

[wadaye]

Re: VHDL, Verilog

VHDL is ada-like and VERILOG is C-like, so they have meny difference

from the Lanuage view.

But both of them are HDL, so their object is same, and you should have

plan your the gate netlist when you coding your design by RTL.

 

[zanov]

VHDL, Verilog

There is a tool good for begginers which does translation between them I find it somewhat good for simple programs
**broken link removed**

 

[saberbf]

Re: VHDL, Verilog

verilog is more simple than VHDL,
it's a c-like HDL language,
you will enjoy its simplicity.

 

[Daneshgar]

Re: VHDL, Verilog

VHDL is the VHSIC Hardware Description Language. VHSIC is an abbreviation for Very High Speed Integrated Circuit. It can describe the behaviour and structure of electronic systems, but is particularly suited as a language to describe the structure and behaviour of digital electronic hardware designs, such as ASICs and FPGAs as well as conventional digital circuits.

VHDL is a notation, and is precisely and completely defined by the Language Reference Manual ( LRM ). This sets VHDL apart from other hardware description languages, which are to some extent defined in an ad hoc way by the behaviour of tools that use them. VHDL is an international standard, regulated by the IEEE. The definition of the language is non-proprietary.

VHDL is not an information model, a database schema, a simulator, a toolset or a methodology! However, a methodology and a toolset are essential for the effective use of VHDL.

Simulation and synthesis are the two main kinds of tools which operate on the VHDL language. The Language Reference Manual does not define a simulator, but unambiguously defines what each simulator must do with each part of the language.

VHDL does not constrain the user to one style of description. VHDL allows designs to be described using any methodology - top down, bottom up or middle out! VHDL can be used to describe hardware at the gate level or in a more abstract way. Successful high level design requires a language, a tool set and a suitable methodology. VHDL is the language, you choose the tools, and the methodology... well, I guess that's where Doulos come in to the equation!

Verilog is a Hardware Description Language; a textual format for describing electronic circuits and systems. Applied to electronic design, Verilog is intended to be used for verification through simulation, for timing analysis, for test analysis (testability analysis and fault grading) and for logic synthesis.

The Verilog HDL is an IEEE standard - number 1364. The standard document is known as the Language Reference Manual, or LRM. This is the complete authoritative definition of the Verilog HDL.

IEEE Std 1364 also defines the Programming Language Interface, or PLI. This is a collection of software routines which permit a bidirectional interface between Verilog and other languages (usually C).

One important note: Don't confuse Verilog HDL with the Verilog-XL family of simulators. In the mid-80's, Gateway Design Automation developed a logic simulator, Verilog-XL, to simulate designs described using their proprietary Verilog HDL. Cadence have since bought Gateway and retained the Verilog-XL simulator, but the language, Verilog HDL, is now maintained by Open Verilog International (OVI). More on Verilog's history in the next Backgrounder article. In all of the pages on this Web site, when we refer to Verilog, we mean the HDL not the simulator.

Today, there is one and only one Verilog HDL. There are now many Verilog-related EDA tools available: formal verification tools, cycle-based simulators, logic synthesisers, timing analysers and ESDA design entry tools with Verilog support. There are of course slight differences between these tools in the aspects of the Verilog HDL that are supported. Not all simulators support the full Verilog HDL, for example.

Finally, VHDL is not an abbreviation for Verilog HDL - Verilog and VHDL are two different HDLs. They have more similarities than differences, however.

 

[sonal]

VHDL, Verilog

VHDL was originally developed at the behest of the US Department of Defense in order to document the behavior of the ASICs that supplier companies were including in equipment. That is to say, VHDL was developed as an alternative to huge, complex manuals which were subject to implementation-specific details.

The idea of being able to simulate this documentation was so obviously attractive that logic simulators were developed that could read the VHDL files. The next step was the development of logic synthesis tools that read the VHDL, and output a definition of the physical implementation of the circuit. Modern synthesis tools can extract RAM, counter, and arithmetic blocks out of the code, and implement them according to what the user specifies. Thus, the same VHDL code could be synthesized differently for lowest cost, highest power efficiency, highest speed, or other requirements.

VHDL borrows heavily from the Ada (programming language) in both concepts (for example, the slice notation for indexing part of a one-dimensional array) and syntax. VHDL has constructs to handle the parallelism inherent in hardware designs, but these constructs (processes) differ in syntax from the parallel constructs in Ada (tasks). Like Ada, VHDL is strongly-typed and case insensitive. There are many features of VHDL which are not found in Ada, such as an extended set of Boolean operators including nand and nor, in order to represent directly operations which are common in hardware. VHDL also allows arrays to be indexed in either direction (ascending or descending) because both conventions are used in hardware, whereas Ada (like most programming languages) provides ascending indexing only. The reason for the similarity between the two languages is that the Department of Defense required as much as possible of the syntax to be based on Ada, in order to avoid re-inventing concepts that had already been thoroughly tested in the development of Ada.

The initial version of VHDL, designed to IEEE standard 1076-1987, included a wide range of data types, including numerical (integer and real), logical (bit and boolean), character and time, plus arrays of bit called bit_vector and of character called string.

A problem not solved by this edition, however, was "multi-valued logic", where a signal's drive strength (none, weak or strong) and unknown values are also considered. This required IEEE standard 1164, which defined the 9-value logic types: scalar std_ulogic and its vector version std_ulogic_vector.

The second issue of IEEE 1076, in 1993, made the syntax more consistent, allowed more flexibility in naming, extended the character type to allow ISO-8859-1 printable characters, added the xnor operator, etc.

Minor changes in the standard (2000 and 2002) added the idea of protected types (similar to the concept of class in C++) and removed some restrictions from port mapping rules.

In addition to IEEE standard 1164, several child standards were introduced to extend functionality of the language. IEEE standard 1076.2 added better handling of real and complex data types. IEEE standard 1076.3 introduced signed and unsigned types to facilitate arithmetical operations on vectors. IEEE standard 1076.1 (known as VHDL-AMS) provided analog and mixed-signal circuit design extensions.

Some other standards support wider use of VHDL, notably VITAL (VHDL Initiative Towards ASIC Libraries) and microwave circuit design extensions.

In June 2006, VHDL Technical Committee of Accellera (delegated by IEEE to work on next update of the standard) approved so called Draft 3.0 of VHDL-2006. While maintaining full compatibility with older versions, this proposed standard provides numerous extensions that make writing and managing VHDL code easier. Key changes include incorporation of child standards (1164, 1076.2, 1076.3) into the main 1076 standard, an extended set of operators, more flexible syntax of 'case' and 'generate' statements, incorporation of VHPI (interface to C/C++ languages) and a subset of PSL (Property Specification Language). These changes should improve quality of synthesizable VHDL code, make testbenches more flexible, and allow wider use of VHDL for system-level descriptions.

 

[The Joy of Electronics]

Re: VHDL, Verilog

Well... I suggest that u study VHDL. Its becomming more and more widespread these days. As ur first question was answered properly, I wont repeat them.