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Recent content by chandra3789

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    Layout of gain boosted op amp!

    it is around 1.2mV.......it is very high but the convergence occured only at that offset.....i dont know why......it is not matching with the theoretical calculations.....but the convergence occured only when i did the DC sweep in a very small range.....anyway my job is done....:) thanks once...
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    Layout of gain boosted op amp!

    Sir, i am very glad. It was a great help. Thanks a lot. your idea of DC sweeping in a very small range worked. thanks once again....
  3. C

    Layout of gain boosted op amp!

    I have tried that also but strangely the two outputs are never reaching the desired output voltage(900mV). There is no convergence. Ok let me check it again...
  4. C

    Layout of gain boosted op amp!

    I tried with CMFB circuit also....the result is the same....... yeah it won't be a problem in negative feedback configuration but the problem i have to show, in my thesis, comparison between schematic and post layout AC simulation results . Because of this non ideality the output voltages are...
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    Layout of gain boosted op amp!

    are you saying that the offset will be eliminated when the op amp is placed in closed loop feedback configuration , no matter how large the offset is? ---------- Post added at 00:59 ---------- Previous post was at 00:57 ---------- thanks for your reply....let me check it...... ---------- Post...
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    Layout of gain boosted op amp!

    Actually the CMFB circuit i am using is a switched capacitor based one....but my question is CMFB takes care of the output node voltages if either both rise or both fall i.e., common mode...but if one node rises and the other falls then how will the CMFB help?....please help me...
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    Layout of gain boosted op amp!

    hi friends, i am trying to do the layout of gain boosted op amp for use in my pipelined ADC. It is a fully differential one with two auxiliary op amps one with NMOS input pair and the other with PMOS input pair. The schematic results of the op amp are good and i started the layout. The problem i...
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    Problem with Voltage reference of ADC

    Yeah , let me give more details...... first of all the architecture i am using is a pretty standard one.it is shown below in the circuit switch S3 connects capacitor Cs to either Vref+ or Vref- or VCM(0 without common mode voltage). The selection of the mux will be based on the output of the...
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    Problem with Voltage reference of ADC

    Hi friends.. i have a big problem with the reference voltage which i have to supply to the pipelined ADC, i have designed, on chip.I have generated the two reference voltages 1.3 and 0.5 Volts(with a common mode voltage of 0.9 V) through low voltage band gap reference circuit. I have to supply...
  10. C

    Off the chip Voltage Reference!

    Actually i need two reference voltages of 0.5 volts and 1.3 volts with a common mode voltage of 0.9 volts for a 1.8V supply .....will the reference i take off the chip be noisy?....are there any instances where reference voltages are taken off chip?
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    Off the chip Voltage Reference!

    hi members..... i designed a 10 bit pipelined ADC which is working at 100 MSPS. I am actually planning for a tape out. For the ADC i need a differential reference voltage. It has to be very precise. I tried to design an on chip band gap reference circuit. The reference voltage generation is done...
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    Charge Distribution Comparator!

    hi i am designing a 10 bit pipelined ADC with 1.5 bit per stage architecture. Since i am not using a sample and hold in the front end, i have to go for a charge distribution (switched capacitor) kind of comparator for path matching. The comparator i am using is shown below. I have few problems...
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    Testing a pipelined ADC!

    Also, while doing transient noise during transient analysis in spectre it asked for noisefmax and noise fmin.....what values should i give?...plz tell me...
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    Testing a pipelined ADC!

    hi folks. i am trying to test the 10 bit pipelined ADC schematic i designed. The procedure i am following for finding the SNDR is " take a sinusoidal input signal nearer to full scale range.Using an ideal DAC reconstruct the signal. Plot its FFT ,say for 1024 points,take those values and find...
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    Gain Boosting folded cascode op amp!

    frnds we all know that gain boosting technique enhances the gain without affecting the frequency response.But gain boosting gives rise to two doublets one due to each auxiliary amplifier.Thier frequency also affects the settling time....... also fast doublets will not affect the performance...
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