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Testing a pipelined ADC!

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chandra3789

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hi folks.
i am trying to test the 10 bit pipelined ADC schematic i designed. The procedure i am following for finding the SNDR is " take a sinusoidal input signal nearer to full scale range.Using an ideal DAC reconstruct the signal. Plot its FFT ,say for 1024 points,take those values and find SNDR, THD, SFDR , SNR from matlab by giving those codes as inputs."
what i did was i did transient simulation ,using cadence spectre, of the schematic to find the reconstructed signal. I didn't enable transient noise option during the simulation. So does this mean the SNDR i got with this simulation is without noise?.For finding the exact SNDR what i should i do?plz help me.......
also for simulating 10.5 microseconds cadence spectre is taking about 9 hours which is very long but there no convergence issues either. Is it because of the bulkiness of the circuit or any other problem?...
Does spectre really take so much time for such kind of simulaitons?...plz help me....
 

Also, while doing transient noise during transient analysis in spectre it asked for noisefmax and noise fmin.....what values should i give?...plz tell me...
 

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