chandra3789
Member level 1
hi
i am designing a 10 bit pipelined ADC with 1.5 bit per stage architecture. Since i am not using a sample and hold in the front end, i have to go for a charge distribution (switched capacitor) kind of comparator for path matching. The comparator i am using is shown below. I have few problems with this comparator.
1. The trip point of the comparator is not proper.
2. The input of M1 is Vin+ and Vref+ or Vin+ and Vref- ? i got this doubt because while charge transfer between the plates of the capacitors there will be an inversion.
3.Also i think the outputs Vo+ and Vo- are given opposite.
plz explain me clearly......the comparator is not working.....
i am designing a 10 bit pipelined ADC with 1.5 bit per stage architecture. Since i am not using a sample and hold in the front end, i have to go for a charge distribution (switched capacitor) kind of comparator for path matching. The comparator i am using is shown below. I have few problems with this comparator.
1. The trip point of the comparator is not proper.
2. The input of M1 is Vin+ and Vref+ or Vin+ and Vref- ? i got this doubt because while charge transfer between the plates of the capacitors there will be an inversion.
3.Also i think the outputs Vo+ and Vo- are given opposite.
plz explain me clearly......the comparator is not working.....
