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Thanks for reply. Why? Because I think if I use the minimum length for the dummy, the size of the cell will be smaller than that use the same size. Then when you connect these cells, it may use long wires to connect them, therefore the parasitic capacitance will increase.
CDZ
Hi Everyone,
For the dummy size, should I use the minimum length of the technology or use the same length of the transistors that I will put the dummy beside? For example, in the current mirror in 90nm, the transistor is 3/0.4(W/L), when I put the dummy beside this transistor, the size of dummy...
Yes, for differential signal there is no crosstalk. But if there are several pairs of differential signals, then there is crosstalk between the differential signals. You mentioned that the trace is close enough for CMMR. Is there any typical value for the signals at a few GHz?
Thanks.
CDZ
Thanks for reply. That is true, if it is too close, then the capacitance between the traces is large and the crosstalk will increase. But if it too far, the CMRR performance will decrease and also the area will increase, therefore the cost may increase. Does the distance has relation with the...
Hi Thanks for reply,
Maybe my question is not clear. Sorry about that. [/img] I upload the figure to help me explain what's my question. the current will decide the width(W) of the trace A and B. My question is: for the speed of few GHz, what's the distance between the trace A and B (d in the...
Hi All,
I have a question about the layout of IC. For high speed differential signals (few GHz to 10GHz), I know the width depends on the current of the signals, but what is distance between these trace? does this related to the width of the trace?
Thanks in advance
CDZ
Hi All,
I use cadence for the IC layout. it is no problem at the beginning. but after I changed the schematic and return the layout. In order to update the netlist and add new components, in the layout, tool -> Layout XL. However, the schematic is not editable and schematic opened is still the...
Hi all,
I design a circuit operating at 10GHz and finished layout. Now I want to add the pad and consider the package. Does anyone know which package and pad (the size) I can use for 10GHz and where to get the model for the package and the pad. I am use 90nm technology.
Also someone told me...
Re: post simulation
Hi Blackuni,
Thanks for reply. I am use Spectra in Cadence. How to use Spice or fast Spice in Cadence.
For the RC reduction, you mean it will be not huge in accuracy for digital circuit. How about for the speed of 10GHz circuit. because this circuit is applied to 10 GHz...
Hi all,
I am using 90nm technology. After I use PLS and create the config view to do the simulation. In the AE, it is no problem that the ti run fast enough for just a few cells. After I want simulate the whole circuit, it because very small. In my circuit, there are 8 DFFs, 8 XOR and 16 Buffer...
Hi all,
I use calibre to do the PLS then LVS. there is no error. But the PLS(DSPF with IRdrop) to do the extract, it generated the following view: PLS_DSPF_INCLUDE, PLS_RCMAX_RCc, pls_dspf_power, pls_dspf_signal, pls_ideal, pls_spectre_rcmax_rcc. My question, after that how can do the...
post layout simulation
Hi All,
I have problem in the PLS. Before I use the diva to do the DRC and LVS then do the extracted. after that the tools generated the extracted view(it can be seen in the lib manager). to do the PLS, just change the stop view list. Now I am using the 90nm and the...
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