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Recent content by cashen224

  1. C

    clock speed for different memory bit width

    Dear Experts, I have a doubt about the max achievable clock frequency for different bit width of BRAM. For example I am using the Xilinx kintex7 device and would like to generate a memory with data widths of 1024 bits (one line contains 1024 bits). I have two options: 1. Instantiate a BRAM...
  2. C

    setup time violation in post layout simulation

    Thanks for the hint. 1) For the timescale, I checked and didn't find anything abnormal. Actually the clock period from the waveform is what I am looking for. 2) For the backannotation. Do you mean send to sdf file generated from SOCEncounter to the PT. If yes, I did so and the PT gives me...
  3. C

    setup time violation in post layout simulation

    Hi, Do you mean setting this: set_false_path. No I didn't do anything with it.
  4. C

    setup time violation in post layout simulation

    Dear experts when I use ncsim for post layout simulations, the tools through some setup time violation warnings and indeed I have X states in the waveform and the total design messed up. however, after P&R using SOC encounter, the SOC encounter shows no setup time violations with pretty large...
  5. C

    errors when using PrimeTime-PX

    Thanks for all the helps. I just realized that there is a version mismatch between DC and PT. I used newer version of DC than PT.
  6. C

    errors when using PrimeTime-PX

    Hi I am a new comer in ASIC design. I am now trying to use PrimeTime-PX for (post-synthesis) timing analysis and power estimation. I saw a lot of errors like following error message while executing PT: "Error: No net timing arc from pin 'U555/Q' to pin 'path_metric_compute/add_87/U1_14/B'...
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