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hi guys, i have project about adaptive filter, i built a model in system generator based on hldcoderlms,but when i start with first tap of filter the result between hdl coder(simulink matlab) and my model (on system generator) is incorrecrt (or i can say wrong), but i dont know why, please help...
hi all,t'm stuck because i don't know how to generate character from rom to display and how to generate locaiton of character from ram to display,could you sugesst for me.please
hi guys,i have a problem that i don't understand about code ROM for VGALIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
ENTITY Char_ROM IS
PORT( character_address : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
font_row, font_col : IN...
hi guys,i search on gg but all vesion is very big size,so i can't download them,my teacher suggets that i find version 12.1,but all link on gg is deleted or not mediafire,so if anyone have link in mediafire,please help me
i wrote code about flip flop D,and i have a problem
[PHPlibrary ieee;
use ieee.std_logic_1164.ALL;
use ieee.std_logic_arith.ALL;
use ieee.std_logic_unsigned.ALL;
entity d_ff is
port ( d : in std_logic;
clk : in std_logic;
clr : in std_logic;
pr : in std_logic;
q: buffer...
hi guys.i wrote code for adder 4 bit using '+" and '&' ,and i have error like thislibrary ieee;
use ieee.std_logic_1164.ALL;
use ieee.std_logic_arith.ALL;
use ieee.std_logic_unsigned.ALL;
entity add4 is
generic (N: natural := 32);
port ( A : in std_logic_vector(2 downto 0);
B : in...
well,i want to know how to ROM and RAM work in vga controller to display text character,i read the book of vhdl example but i ca't understand all of them,so cuold yoi explain again for me,thanks,i work in fpga spartan
i have a homework that i have to code the decoder 2_4 like ic 74139,then i found the code for this
library ieee ;
use ieee.std_logic_1164.ALL;
entity decoder_2_4 is
port( a : in std_logic_vector(1 downto 0);
en : in std_logic;
y : out std_logic_vector(3 downto 0)
);
end entity...
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