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You can place the dummy device with minimum spacing to the actual device..
In case of less area,
Make the dummy device with 1. Same width similar to the actual device.
2. Minimum length..
The above thing is applicable if you're placing...
Hi all,
In the post layout extraction ( pex extraction ), if there's any problem occurs in pex means, we need to vary ( increase or decrease the resistance & capacitance ) in some signal lines..
I think we can reduce the resistance by using an higher metal instead of using metal 1 or...
Hi erikl,
I just wanna know the reason why we shouldn't connect the source of pmos to the bulk.. What'll be the effect if we connect so.. ?
Can you please explain this in detail (or) provide me any links...
Also i've a doubt that,
What is the need of guardring ( NWell & PTAP ) & what is it...
Yes, I agree that psub2 layer is a virtual layer..
I'll explain it in some 2 conditions,
1.
Different Grounds--> ex, vssd & vssa :
You'll have different grounds only in your block levels as vssa & vssd.. In that time you'll use psub2 layer to clear your LVS. But In the topmost level (Dphytop...
Yes, you're right..
In order to isolate 3 transistors with bulk connected to corresponding sources, you've to enclose each transistor with NWell guardring.. Only by doing that, you can able to seperate the 4th terminal (bulk)..
You'll get LVS error only by doing above thing,..
You've to draw an...
Thanks erikl and dich free_bird,
" Mask/photoresist (lithography) resolution isn't good enough to reproduce such tiny structures. DRC would tell you a violation. "
From the Above statement (from erikl), I 've understood that,
The metals in the following snaps have no...
Thanks for your response..
I can't view your attachment, It is showing the error message as
" Invalid Attachment specified. If you followed a valid link, please notify the administrator"...
Can you send an valid image again..
Thanks erikl
In the snap what i've attached has the metal not connected properly ( metal is not stopped in the place where it should be ) , Will it cause any problem?
Then, Coming to notches.....
Can u explain me with any images I.e., Snaps of -- metals having notches.
Also i need to know...
Hi all,
Can anyone please explain me about the effect of notches in layout ? Or kindly provide me any docs or any link.
I've attached the layout view for example.. Here the Metal 1 layer is having notch and DRC will not detect this as an error...
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