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Thank you, In my if-elsif code above, I added an else conditions and all those Latch related warnings went away :)
Didn't know about this function before and seems to be very appropriate for my task. Thank you.
I wrote a small FSM (Mealy Machine) transition table design using VHDL and I'm using ISE(Xilinx Design tool) for synthesis. The synthesis goes fine but, It also throws some warning messages. It seems that my code is generating some latches, but I couldn't find a way to remove it.
The input X...
Thank you. So on one hand, it may save time in verification process(No need to rewrite the testbench in the same language as is the design) and on the other it can cause increased cost from the tools persepective(The need to have such a Simulator). But are there any difference in the simulaion...
Hi All,
Sometime back in this forum I had asked some queries pertaining to Behavioural modelling of an elevator-controller. I succeeded in doing the required design in VHDL and the same in Verilog as well. While doing this exercise, I also came to know that it is possible to use a VHDL...
Yes, I'm running this on a simulator and I do have the testbench as well. As you said, I'll now dig more into the testbench and the waveform to find the problem.
Probably you are right, but I've to live with this for now.
The purpose of this task was not to learn the digital circuits, rather learn the different objects such as processes, signals, variables etc in the VHDL world and use those to model a behaviour of an elevator.
Hi All,
I'm a newbie in the digital modelling world and I'm really keen on learning it. As part of the college curriculum, i've been given a task to model an elevator whose functioning is mentioned **broken link removed**, I've been working on it, but haven't been successful so far, as I had no...
I'm still trying to get rid of my "C" way of approaching the Modelling tasks, as In past I've mostly used "C". I have spent a considerable time in thinking how to solve such kinds of modelling problems and have not been much successful so far. It'll help me a lot if you suggest me some books or...
Hi All,
I'm working on modelling of elevator control and I'm trying to come up with two separate process for tackling the different requirements for this particular elevator control. The main idea that I have is that One process will continuously snoop for the requested floor by ORing the...
Thank you for your reply. I've now changed the design model as:
library ieee;
use ieee.std_logic_1164.all;
entity flip_flop is
port ( d: in std_logic;
clk: in std_logic;
ce: in std_logic;
pre, clr: in std_logic;
q, q_n: out std_logic );
end entity flip_flop;
architecture behave of...
This negative edge triggered flip flop has both active low and active high output ( q and q_n), and as VHDL will not allow me to put a output signal on the right side of the assignment (<=) operation. i.e.
q_n <= not q; -- would be wrong
Therefore I'm using a temporary signal and for the...
Thank you for pointing out the missing clk signal generation. I've now added a clock signal generator process and have also modified the testbench a little. With this changed testbench, I never see the output "q" to become high("1") and is rather underfined or zero all the time.
The modified...
Hi,
I'm referring this book from Peter J Ashenden on Digital Design and to make my understanding solid, I'm trying to write the testbench and verify my model, However, As I've already posted this in past that, I'm really struggling with test bench at this moment, therefore would really...
Thank you for the pointers.
As of now, one of the biggest problem that I'm facing is the lack of skills to write a decent testbench for simuation and testing purpose of my design. For example, I recently came across the "assert" feature, and now after reading a little, I understood how to use...
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