[SOLVED] Remove Latches from the design

[bitprolix]

I wrote a small FSM (Mealy Machine) transition table design using VHDL and I'm using ISE(Xilinx Design tool) for synthesis. The synthesis goes fine but, It also throws some warning messages. It seems that my code is generating some latches, but I couldn't find a way to remove it.

The input X is the external input to the design which I plan to map using User Constrained file to some switches on my target FPGA board, So should I ignore the first Warning message(shown in bold below). The warning message are shown below.

WARNING:Xst:647 - Input <X> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:737 - Found 1-bit latch for signal <Y<3>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Y<2>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:1426 - The value init of the FF/Latch Y_2 hinder the constant cleaning in the block lab5fsm.
You should achieve better results by setting this init to 1.
WARNING:Xst:1293 - FF/Latch <Y_3> has a constant value of 0 in block <lab5fsm>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <CURRENT_STATE_1> has a constant value of 0 in block <lab5fsm>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1426 - The value init of the FF/Latch Y_2 hinder the constant cleaning in the block lab5fsm.
You should achieve better results by setting this init to 1.
WARNING:Xst:1293 - FF/Latch <Y_3> has a constant value of 0 in block <lab5fsm>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <CURRENT_STATE_1> has a constant value of 0 in block <lab5fsm>. This FF/Latch will be trimmed during the optimization process.

The complete VHDL code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity lab5fsm is
	port (X: in STD_LOGIC_VECTOR(2 downto 0);
			CLK: in STD_LOGIC;
			RESET: in STD_LOGIC;
			Y: out STD_LOGIC_VECTOR(3 downto 0));
end lab5fsm;

architecture Behavioral of lab5fsm is
	-- define the state of the FSM
	type STATE is (A1, A2, A3, A4);
	
	-- signals to manage the current state and next state
	signal CURRENT_STATE, NEXT_STATE: STATE;
	
begin

P1: process (RESET, CLK)
begin
		-- Initial state is A1 and the state changes only
		-- on rising edge of the clock.
		if (RESET = '1') then
			CURRENT_STATE <= A1;
		elsif (CLK'event and CLK='1') then
			CURRENT_STATE <= NEXT_STATE;
		end if;
end process P1;

P2: process(CURRENT_STATE, X) 
	begin
	case CURRENT_STATE is
		when A1 =>
			Y <= "0111";
			NEXT_STATE <= A2;
		when A2 =>
			if (X = "00-" ) then
				Y <= "1100";
				NEXT_STATE <= A3;
			elsif (X = "10-" ) then
				Y <= "0010";
				NEXT_STATE <= A1;
			elsif (X = "-10") then
				Y <= "1110";
				NEXT_STATE <= A1;
			elsif (X = "--1") then
				Y <= "0110";
				NEXT_STATE <= A1;
			end if;
		when A3 =>
			if (X = "-0-" ) then
				Y <= "1110";
				NEXT_STATE <= A4;
			elsif (X = "-1-") then
				Y <= "0111";
				NEXT_STATE <= A1;
			end if;
		when A4 => 
			if (X = "1--" ) then
				Y <= "0111";
				NEXT_STATE <= A1;
			elsif (X = "0--") then
				NEXT_STATE <= A3;
			end if;
		when others =>
				Y <= "XXXX";
	end case;
end process P2;

end Behavioral;

Transition table, based on which I've written the above VHDL code is also attached here.
View attachment transition-table.pdf

 

[TrickyDicky]

Its bacuase you do not assign NEXT_STATE and Y in all cases. If you use the 2 process state machine style, you need to enasure all outputs are assigned in ALL cases.
And you will have problems in simulation, as although '-' is dont care, you will only get a match on X if is exactly "-01" or whatever. "001" will not match. You need to use the std_match function.

 

[bitprolix]

Its bacuase you do not assign NEXT_STATE and Y in all cases. If you use the 2 process state machine style, you need to enasure all outputs are assigned in ALL cases.

Thank you, In my if-elsif code above, I added an else conditions and all those Latch related warnings went away

And you will have problems in simulation, as although '-' is dont care, you will only get a match on X if is exactly "-01" or whatever. "001" will not match. You need to use the std_match function.

Didn't know about this function before and seems to be very appropriate for my task. Thank you.