Beginner's guide for writing testbenchs

[bitprolix]

Hi,

I've recently ( a week back) started VHDL programming and I'm trying to learn by designing simple behavioural programs, but to test those designs, It seems that I've to write the testbench myself as well. It would be very helpful to me if you can give me some ideas on things that one needs to consider while writing simple testbenches, or is there any utility/tool that can generate a testbench for my design ? For example, a behavioural model of simple thermostat design, where the thermostat turns ON and Off, based on the difference between the desired and actual temperature is as follows:

entity Thermostat is
  port (  desired_temp, actual_temp: in integer;
          result: out boolean);
end entity Thermostat;

architecture Controller of Thermostat is
begin
  myprocess: process (desired_temp, actual_temp) is
  begin
    if desired_temp < actual_temp - 2 then
      result <= true;
    elsif desired_temp > actual_temp + 2 then
      result <= false;
    end if;
  end process myprocess;
end architecture Controller;

Now to write the testbench and then simulate the design, how should I proceed? At this moment a more explicit direction/help would be extremely helpful to me.

 

[ads-ee]

VHDL isn't a programming language, it is a hardware description language. Instead of describing a design in schematics a design is described using constructs that superficially look like software.

I bring this up as your "hardware" design requires a subtraction and a comparison in series followed by another addition and comparison in series to produce the priority encoded result. Unless the design uses a very slow clock frequency this controller will have difficulty making timing in HW. I figure you probably weren't aware or weren't thinking about what your circuit would synthesize into.

About the testbench, I generally write transaction based testbenches using tasks (I usually write code in Verilog). The tasks themselves are embedded in a bunch of BFMs (Bus Functional Models) which emulate the interface I'm stimulating. The testcase is the most software like code in Verilog I write as it "runs" the testcase using tasks like tWRITE(`ADDR, write_data); and tSEND_DATA(num_bytes);. So the testbench contains instantiated BFMs the UUT and any clock and reset models. On occasion I use file I/O functions to read data from a file to stimulate the design and capture output data to another file. Maybe this will give you some ideas of how to start.

Regards

 

[bitprolix]

VHDL isn't a programming language, it is a hardware description language. Instead of describing a design in schematics a design is described using constructs that superficially look like software.

I bring this up as your "hardware" design requires a subtraction and a comparison in series followed by another addition and comparison in series to produce the priority encoded result. Unless the design uses a very slow clock frequency this controller will have difficulty making timing in HW. I figure you probably weren't aware or weren't thinking about what your circuit would synthesize into.

First of all, Thank you for the pointers and sorry for not being active here for sometime. I was neck deep in university assignments.

About the testbench, I generally write transaction based testbenches using tasks (I usually write code in Verilog). The tasks themselves are embedded in a bunch of BFMs (Bus Functional Models) which emulate the interface I'm stimulating. The testcase is the most software like code in Verilog I write as it "runs" the testcase using tasks like tWRITE(`ADDR, write_data); and tSEND_DATA(num_bytes);. So the testbench contains instantiated BFMs the UUT and any clock and reset models. On occasion I use file I/O functions to read data from a file to stimulate the design and capture output data to another file. Maybe this will give you some ideas of how to start.

This is quite a lot for me to grasp as this moment, because, first of all, i have not written even a single testbench so far (I've been testing my design against testbench provided by someone else) and second i've not touched verilog yet. However my understanding about digital modelling over the last couple of weeks have improved a little, I'll come back to your solution, after gaining more insight on digital modelling.

 

[TrickyDicky]

As a beginner, you're better off starting with the very basics - how to write HDL that synthesises into logic, and understanding how that works. Moving onto complicated BFMs can come later (much much later). At first write good HDL that synthesises, and testbenches that generate simple inputs, usually using file IO.

You can also write complicated BFMs in VHDL too (but more people do it in System Verilog as thats what most companies do).

 

[bitprolix]

As a beginner, you're better off starting with the very basics - how to write HDL that synthesises into logic, and understanding how that works. Moving onto complicated BFMs can come later (much much later). At first write good HDL that synthesises, and testbenches that generate simple inputs, usually using file IO.

You can also write complicated BFMs in VHDL too (but more people do it in System Verilog as thats what most companies do).

Thank you for the pointers.

As of now, one of the biggest problem that I'm facing is the lack of skills to write a decent testbench for simuation and testing purpose of my design. For example, I recently came across the "assert" feature, and now after reading a little, I understood how to use it in the design. However, because of lack of knowledge on writing testbenches, I'm not able to test my design. This is definetely one of the biggest hurdle for me right now. Are there any beginners level books on writing testbenches in VHDL too ?