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Recent content by bharath_k

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    Subthreshold op amp design

    Hello Everyone, I have a question regarding designing a op-amp is subthreshold region. I have found few papers which are really helpful but I am still not getting clear idea. In the above circuit how to I design M3, M4 and M5? In op amps biased in saturation region we typically use ICMR+...
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    [SOLVED] CMOS inverter feedback

    Hi Klaus, Thanks for the reply. It is simulation in cadence. The first stage is designed for a bias of 900 mV and subsequently following stages are designed for the output voltage generated from previous stage. I just ran a dc simulation and anotated the node voltages. Thanks, Bharath
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    [SOLVED] CMOS inverter feedback

    Hello Everyone, I am trying to generate a sort of digital signal from a random input. For now I am using a random 1/f signal generated from Matlab with amplitude of 1 nV as input to my inverter. I have a six stage inverter with a gain of about 37 dB in each stage and at the end I am getting a...
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    Intrinsic noise of a MOSFET

    Thanks a lot for your detailed analysis. After a lot of search I found in latest version of Cadence we can do transient noise analysis. So I would probably try this.
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    Intrinsic noise of a MOSFET

    Hello everyone, I want a random noise generator. I will feed the random noise to a comparator and then use this signal to trigger a oscillator. So can I use the intrinsic noise a MOSFET as my noise source? if so how do I simulate this? Thanks, Bharath
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    Current reference circuit

    Sadly off chip resistor is not allowed. Instead I was trying to use gate leakage current of NFET and achieve the required high resistance. But for the technology I am using the gate leakage has too much changes across corners.
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    Current reference circuit

    Hi Sunny, current source.
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    Current reference circuit

    Hello Everyone, I am trying to design a current reference circuit. I want a current of about 20 pA current and the technology I am using is 180nm EM microelectronic. Unfortunately I am running out of ideas. I have tried using a diode connect NFET with vgs=0 to use the leakage current and tried...
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    DC-DC Switched-Mode Power Supply System

    Hello All, I designed a system to convert from 1.8V to 3.3V. I have the schematic diagram as shown below. I am running corner analysis and it passes all the corners except in SS_pre as shown below. I get ripples. When I see the switching of the comparator is slow. From what I can see either...
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    Charge pump topology

    Thanks a lot. I will work on this and let you know the result.
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    Charge pump topology

    Hi Brad, Thanks for your reply. May be I didn't explain my application clear. I don't want an oscillating circuit. I want a DC-DC converter. The application where this charge pump to be used is for Neurostimulation. Thanks.
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    Charge pump topology

    Hi everyone, I have a task to design a charge pump to generated a output voltage of 3.3 V from 0.8 V supply with load current of 8 mA in 22nm technology. I started off with a Dickson charge pump and also tried pelliconi charge pump. But in both cases the output current is in micro amperes...
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    Designing the output stage class ab

    I know Vth of the device and not sure whether I can share it. So gave the range. I have found out a way to design. Your inputs were very valuable :)
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    Simulation of output stage

    Okay I will reconfirm with my supervisor and check for different architecture.
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    Simulation of output stage

    Here is the architecture given to me.
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