[SOLVED] CMOS inverter feedback

[bharath_k]

Hello Everyone,

I am trying to generate a sort of digital signal from a random input.

For now I am using a random 1/f signal generated from Matlab with amplitude of 1 nV as input to my inverter. I have a six stage inverter with a gain of about 37 dB in each stage and at the end I am getting a random digital signal going from 0 to 1.8V.

The following table shows the bias voltage in each stage and I got my desired output.

Vout1	869m
Vout1_1	879.5m
Vout1_2	932.2m
Vout1_3	819.8m
Vout1_4	867.5m
Vout1_5	991.2m

But when I gave a different noise signal( It is still 1/f and amplitude of 1nv). The bias points have drastically changed which is understandable. Following table shows the bias voltages

Vout1	869m
Vout1_1	879.5m
Vout1_2	933.6m
Vout1_3	718.5m
Vout1_4	1.654
Vout1_5	192.8n

Is there any solution where can I force the inverter stages to be in a particular bias point through feedback? or if any better circuit I can consider to get the desired output?

Thanks,
Bharath

 

[KlausST]

Hi,

I guess it´s rather difficult to help. We don´t see your circuit.
We don´t see how you measured the output voltage.

Is it a pure simulation, or a real circuit?

I guess it´s a problem of proper biasing, proper coupling, frequency of interest, measurement methods....

Klaus

 

[bharath_k]

Hi,

I guess it´s rather difficult to help. We don´t see your circuit.
We don´t see how you measured the output voltage.

Is it a pure simulation, or a real circuit?

I guess it´s a problem of proper biasing, proper coupling, frequency of interest, measurement methods....

Klaus

Hi Klaus,

Thanks for the reply. It is simulation in cadence.

The first stage is designed for a bias of 900 mV and subsequently following stages are designed for the output voltage generated from previous stage.

I just ran a dc simulation and anotated the node voltages.

Thanks,
Bharath

 

[dick_freebird]

For an AC or sparse pulse amplification lineup, I like "autobiased
inverters" with capacitor blocking. I have also used schemes where
a small fed-back inverter serves as a bias reference, and multiple
C-blocked stages (not fed back) receive gate bias through a high
value R (centering them "well enough" but not costing as much
signal, as the Miller-resistor-feedback-inverter.

You'd rather not have DC gain if you aren't looking for DC gain.
For noise measurement you want to determine the lower corner
frequency of interest and then see if a circuit is realizable, that
does it (like, integrating 10Mohm and 10uF ain't it, so forget a
0.01Hz noise-vs-frequency X-axis)