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Re: settling time issue in fully differential opamp
So, It is like the more the value of output resistance or load cap, the higher the settling time is....
What about the values of Rcmfb? Can it be comparable to Rds_p//Rds_n let us say equal values?
I already posted the setup for the otherway...
Re: settling time issue in fully differential opamp
Thanks for the replies ZoOneR, frankrose, and erikl. I got an idea regarding settling time. Now I have one last question regarding this settling time. How do I adjust this settling time? Is there any intuitive way of looking at this so that I...
Re: settling time issue in fully differential opamp
Usage of an opamp is not either of circuits you mentioned. I want to use the fully differential opamp as the noninverting amplifier with the selection of multiple gains (Programmable gain amplifier(PGA)) which amplifies modulated version of...
Re: settling time issue in fully differential opamp
Thank you very much for the reply erikl. I guess, I had doine correct this time. I am posting the snapshots.
If my snapshots are correct, I have two doubts which I want to be cleared.
1) If my complete design (total design which is...
Re: settling time issue in fully differential opamp
Thanks for the reply....
I have simulated the amplifier in CMFB network separately and seen the AC response which is giving sufficient phase margin (approximately 90 degrees) to say that this part is stable. However, when I connect this CMFB...
Re: settling time issue in fully differential opamp
Hi ZoOneR,
Are you suggesting me to redesign the common mode feedback network? Can I get the proper explanation for your answer?
I have designed two-stage fully differential opamp. I took the results and seems every parameter is giving good results except settling time (I believe). To check this, I connected in unity gain configuration and applied the pulse input of 500us (probably, I may be wrong in circuit setup)...
I want to connect the CMFB's output to load of 1st stage of the differential circuit. And CMFB's input is coming from 2nd stage output of differential amplifier.
Hai,
I am designing common mode fully differential two stage opamp. opamp has ben designed whose inputs are fed at NMOS MOSFETs. I have decided to use differential difference common mode feedback circuit (non-resistive). I am confused what type of CMFB would be taken like inputs of CMFB at PMOS...
Thank you very much for the reply.
I have two questions to ask. Can you please answer my questions?
1) Where can be the CMFB placed in two stage fully differential opamp? (Like between the first stage output and gate terminal of current source load of the first stage OR second stage output and...
Now I have come up with the complete fully differential opamp along with common mode feedback network.
I don't know whether my design is right or not.
But I am not able to keep all the MOSFETs in the design in the saturation region.
CMFB part is missing in this FD structure which I know and I am working on that. Can u elaborate what was the next point you are explaining
"You have two "lambda" error terms to
take out and your device lengths are that large.
Might play with offsetting the N load relative to the
P sources on...
Thanks for the reply. I took this relation as a rough guide only to design the structure and got this relation for above kind of op-amp. But I am trying to design the fully differential two-stage opamp. For this, I was not able to achieve that systematic offset relation
see the structure along...
I have a question regarding the systematic offset voltage constraint for designing two-stage opamp.
While designing the Two-stage op-amp, there is a relation to avoid the systematic offset voltage which can be defined for the given op-amp as,
((W/L)4)/((W/L)7)=0.5((W/L)5)/((W/L)6)
What...
I am trying to design the fully differential opamp. I put all the values according to mathematical calculation and put those values in simulator. After some simulation, some transistors are going to linear again against the calculations. I found a very high value of common mode voltage at output...
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