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Hello
Can you please confirm if this is the circuit diagram is correct for Asynchronous Positive edge triggered D flip flop with preset and clear? I am not getting expected results only for 1 condition : when Preset =1, clear=0 -- expected output Q=1 but it shows Q=0.
Can you please advice...
Yes I am not sure either about this either. But I do need to check timing using verilog netlist , .lib (liberaty files) and spectre netlist. Yes the schematics are designed by me .
Hello
Usually in synthesis ( cadence genus tool) we use a verilog netlist, .lib files and perform synthesis to determine the timing paths for a design.
But now I want to perform synthesis / timing analysis using cadence genus tool using an additional spectre netlist( reliability / aging...
Is it possible to use aging netlist in cadence tempus flow in addition to the other regular inputs of tempus (like verilog netlist, .lib etc)to determine timing? Intention is to see the impact of ageing behaviour on tiiming
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Is it possible to use aging netlist in cadence tempus flow...
Thank you @Akshaay. Could you also please let me know is it possible to perform characterization using cadence liberate tool to generate a .lib file using the Aged netlist ( Reliability analysis netlist / aged data) ?
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Thank you @Dominik Przyborowski . Could you also please let...
Hello
Could any one please tell me , can reliability simulation in Cadence ADE be performed on post layout Test bench too? Is it possible to have a netlist which contains PEX- parasitic and ageing/ reliability data in it?
Thanks in advance
B
Hi
I am new to aging simulation using RelXpert. I have few queries:
1. Could anyone please tell me if I could do aging simulation using .lib file obtained after characterization of cells?
2. Model files, NBTI and PBTI files are the inputs needed for aging simulation?
3.And how to analyze...
Hello
I am new to characterization of standard cell Libraries. I am using cadence Liberate tool. I have few queries:
1.what is an av extracted view in cadence ? does it contain RC information, and how can I generate the av extracted file after the layout design?
2. what are the main input...
Hello
I would like to to know if there is an alternate method to do basic evaluation of a silicon chip and read voltage and current signals of a chip without PCB?
Any idea of these methods?
1. is there any individual chip socket for a silicon chip which I could...
Hi
I am new to analog IC design and I am trying to understand the characteristics of class A, AB, C amplifiers and a dc-dc converters.
Is there a standard design for the amplifier and dc-dc converter where I can implement in a cadence schematic tool and run the analysis?
Thanks in advance
BB
Hi
Can anyone please point out the main differences between Finfet and cmos LAYOUT, Device and Layout Challenges , advantages / disadvantages of Finfet?
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