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Recent content by bacbac

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    How to deal with extra, useless bit in FPGA, digital design????

    Hello I don't know if I can discribe to you can understand my problem!? I'm new digital design. During design my FPGA circuit, I want to use signal with same bith length (for example 10 bits). when I put this 10 bits signal to the filter, it produces a 18 bits signal. but there're only few last...
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    Time constraint for big project in FPGA, Quartus II/TimeQuest timing analyzer

    thanks ads_ee!
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    Time constraint for big project in FPGA, Quartus II/TimeQuest timing analyzer

    Hello ads_ee, Thanks for your answer. I still have question that Do I have to care constraint inside blocks FFT, FIR? They are all complicate and generated by mega core function by altera. I don't know their structure. How can I make sure that these blocks work well, do not violate time requirement?
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    Time constraint for big project in FPGA, Quartus II/TimeQuest timing analyzer

    Hello,:oops::oops: I got problem when trying to do my project. It's quite big with some FFT, Filter ... and so on. The result signals are some way getting wrong. I thinks it causes of time violation. I tried to read some documents about time constraint. They all talk about registers. But...
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    Confuse about Inphase and quadrature component BPSK signal.

    I did my Costas loop for BPSK signal in my project. Out put of the loop is BPSK code. I need the BPSK code for next correlator. I realize that from only one branch of the loop (Inphase or quad), I can take BPSK code by comparing with a threshod level. On the internet I found some document...
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    Constrain a type RECORD in VHDL, error!!!!!

    Thanks TrickyDicky,
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    Constrain a type RECORD in VHDL, error!!!!!

    Thanks TrickyDicky! In the program Quartus II, I have chosen Setting/Analysis and synthesis settings/ VHDL input/ VHDL 2008 and OK, It took no change and the error is still exist. Any suggestion?
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    Constrain a type RECORD in VHDL, error!!!!!

    Hi, I have a problem when trying to work with complex number in VHDL. I declare type of RECORD to simulate a complex number without constraint, then I try to constrain it when I using after. Here is my code: library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use...
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