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Hello
I don't know if I can discribe to you can understand my problem!? I'm new digital design.
During design my FPGA circuit, I want to use signal with same bith length (for example 10 bits).
when I put this 10 bits signal to the filter, it produces a 18 bits signal. but there're only few last bits in the 18bits output are really carry information. (first bit is sign, then bit from 17 downto 12 are constantly zero).
Also the filter has gain. I truncate it from bit 18 to 9.
when I put the signal go to a next filter, It agian make 18bits output and then the number of zeros between first bit(signed bit) and last bits increases. And output signal become smaller and smaller.
How can I deal with these zero bits?
I don't know if I can discribe to you can understand my problem!? I'm new digital design.
During design my FPGA circuit, I want to use signal with same bith length (for example 10 bits).
when I put this 10 bits signal to the filter, it produces a 18 bits signal. but there're only few last bits in the 18bits output are really carry information. (first bit is sign, then bit from 17 downto 12 are constantly zero).
Also the filter has gain. I truncate it from bit 18 to 9.
when I put the signal go to a next filter, It agian make 18bits output and then the number of zeros between first bit(signed bit) and last bits increases. And output signal become smaller and smaller.
How can I deal with these zero bits?
