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Recent content by arya.jagadeesh

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    [Moved]: How to do AC analysis of LDO

    Re: How to do AC analysis of LDO Hi, If you are using current source then it will not effect the output pole position as the resistance of ideal current source is infinity but if you use resistor this will come in parallel with your output resistance and may effect output pole position. it is...
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    How to decide current in bandgap

    Hi, How to decide amount of current in bandgap core VREF = vbe +R1(vt ln(n))/r If current is more R1 required is less apart from power and area tradeoff ...is there a deciding factor for how much current we should burn in bandgap core
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    OTA error amplifier in LDO

    yes you can place pass transistor in linear . if load current is very high then it is very difficult to place pass transistor in saturation.As long as gain is there in loop it is ok to place pass transistor to keep in triode. It has its effects on stability and PSRR
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    [Moved]: CS Stage with current-source Load

    mosfet is voltage controlled current source... so situation here is like you have two current sources in series...if you write kcl...some of entering cuurents at particular node is equal to sum of leaving currents..will be true only if values of current sources in series are equal..suppose if...
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    How does an Error amplifier works?

    when both terminal of err amp are same what is your output is common mode output voltage..now on this common mode if you apply some differential signal..change in your output is AVOL times input signal difference
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    how to reduce the effect of pad parasitics on ldo output

    HI, When i tried to find the psrr after applying pad parasitics ...when i apply ac in supply which goes to internal to chip , i am seeing a spike of in my supply just after pad parasitics...how to reduce it. max how many pads i can have in parallel
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    AC response of uncompensated LDO

    Hi have you calculated output pole?
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    AC response of uncompensated LDO

    basically there are 2 poles and one zero(esr zero need to place resistance(10m) in series with output cap ) pole positions 1/(ctotal *rtotal) at every node poles are 1)power fet gate pole 2)output pole location is 1/(cout*{ron*[rf1||rf2]}) ron if power fet in triode or else it is rds for...
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    Capless Ido architecture

    Re: capless ldo architecuture if your output cap is high then you can make o/p pole dominant..with small cap say 100-200p output cap how can we make o/p pole dominant in full load
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    Capless Ido architecture

    capless ldo architecuture Hi Suggest me some capless architectures. how to make err amp pole dominant.I am using miliken compensation and seeing problems in transients..can you suggest me other architectures
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    Verilog: 8-bit Adder Error: The logic does not match a known FF or Latch template

    yes...modified code should work...what is happening is ...assignment statement is, you are driving signal if you are having two drivers to same net it is conflict..instead you can drive it with priority .
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    Verilog: 8-bit Adder Error: The logic does not match a known FF or Latch template

    instead of using output signal in assignment ...take one wire or reg and use it it addition ..and finally asign that to output...may be that will work
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    Current Mirror Zeros

    in any circuit zero comes when there are two paths between same nodes with 180degree phase shift...in case of current mirror gate and drain are externally shorted so one path with no phase shift...and other is due to mosfet action ..gate and drain are 180 degree ...so these two paths give you...
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    Bootstrapping current for bandgap generation

    who decides the amount of startup current
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    thevenin theorem please help

    convert voltage sources with series resistors into current sources with parallel resistors and add currents and find equivalent res..then again use source conversion o
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