Capless Ido architecture

[arya.jagadeesh]

capless ldo architecuture

Hi

Suggest me some capless architectures.

how to make err amp pole dominant.I am using miliken compensation and seeing problems in transients..can you suggest me other architectures

 

[AMS012]

Re: capless ldo architecuture

Making error amp pole dominant always kills the PSRR which is very important spec for an LDO. Why dont you make the output pole dominant.
Also it is very likely that the circuit the LDO is feeding requires some decoupling cap. The decoupling cap also improves LDO stability if you make the output pole dominant.

 

[arya.jagadeesh]

Re: capless ldo architecuture

Making error amp pole dominant always kills the PSRR which is very important spec for an LDO. Why dont you make the output pole dominant.
Also it is very likely that the circuit the LDO is feeding requires some decoupling cap. The decoupling cap also improves LDO stability if you make the output pole dominant.

if your output cap is high then you can make o/p pole dominant..with small cap say 100-200p output cap how can we make o/p pole dominant in full load

 

[erikl]

Re: capless ldo architecuture

Suggest me some capless architectures.

Here are a few links which could be helpful:

EDAboard - capless LDO

A capacitor-free CMOS low-dropout regulator with damping-factor-control frequency compensation

**broken link removed**

Pole-zero tracking frequency compensation for low dropout regulator