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Recent content by arishsu

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    OpenCL host code in Vivado

    Hi all, I am actually working on neural network implementation on Zynq FPGA and I am going with Vivado HLS using OpenCL. I am totally new to OpenCL and a bit confused with how to write host code for the OpenCL kernel. Can anyone help me with this or suggest any resources? Thanks in advance
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    xilinx timing analysis report

    How to set timing constraints and input/output constraints?
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    xilinx timing analysis report

    That means number of clock cycles*clock period? But in the report, the input arrival time before input(or the setup time) is more than clock period. Then how will it work?
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    xilinx timing analysis report

    I need to calculate the time delay required to calculate the output after input is given. how can I calculate that? And what is 'Maximum output required time after clock' mean?
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    xilinx timing analysis report

    Hi I have simulated a multiplier verilog code on xilinx ISE and I got the synthesis report and Post PAR static timing report as shown below. What is actually these terms mean? How can I calculate the total delay of the circuit?
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    working of a charge pump

    How to or where to connect previous and next stage terminals of figure c to figure b and where should I give the enable input?
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    [MOVED] Code for Decimal to Binary conversion using Verilog

    I'm a bit confused because verilog takes input in binary form and gives output also in binary form. We can only display the output in decimal I guess.(Not sure) So, you mean, you have to give a decimal input to the device - like from a keyboard- and to display the output in binary form. right?
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    working of a charge pump

    Can anyone please explain how to connect the switching circuit and timing generation circuit.
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    Spartan 3E LCD verilog code problem

    Anything. A simple hello world program for example.
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    How to reduce usage of bonded IOBs

    Sorry, I don't understand. Is it like using a RAM for storing input/outputs?
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    How to reduce usage of bonded IOBs

    What is actually mean by using a bigger part?
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    How to reduce usage of bonded IOBs

    When I simulated my verilog code, the following warning is shown. WARNING:Xst:1336 - (*) More than 100% of Device resources are used Device utilization summery is as below. These are my input/output parameters. input clk,reset; input[2:0]prec_sel; input[5:0]prec_bit; input[63:0]a,b...
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    Spartan 3E LCD verilog code problem

    I tried to run this code on the fpga, but it is showing some garbage characters. I got this code from the web. Please help me to correct the code. module test_lcd(clk,sf_e,rs,rw,a,b,c,d,e); input clk;//50Mhz onboard clk output reg sf_e;//1 lcd access (0 strataFlash access) output reg...
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    HELP: code for number catcher(number select) implemented in FPGA

    Which language? The counter is free running and whenever number 4 occurs count increases by 1. right?
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    how to convert floating point to integer format using verilog

    Actually I want to display the result in LCD as decimal. It is ok even if I can only display the result separately as exponent, sign and mantissa. And mantissa also can be displayed separately as integer part and fractional part, but in decimal. for example, suppose my result is 1 10000110...
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