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The idea here is that fig C is inserted under each block to connect to Vdd Vcpl and Gnd for each block is in fig B.
This is supposed to optimize propagation delay so the Vdd and Vss switches connected to each other never are on at the same time causing the classic shoot thru problem. Sometimes overlap for <1us is ok but timing changes with temperature for better or worse. so this design is supposed to control the dead time with a Vcpl pulse.
The basic charge pump using transmission gates may be experimented with as well to see how rise times affect device current using a 100mV drop shunt resistor to monitor... such as 10 Ohm. or less.
Run with CC limit to protect the chip in that vendor chip since this has no transition time disable. So you can see the differences with your more discrete circuit.
Short wires, decoupling and short probe ground are all essential to good performance.
The output in Fig B on top right is the Last Stage thus ...
. Next stage output while next stage Input is "Enable"..
And 1st stage in Fig B on left has prev stage in<>out joined with Buffer added to drive input cap on 1st stage.
Thus all switches race around the loop to avoid shorting Vcc to Vdd.
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