xilinx timing analysis report

[arishsu]

Hi
I have simulated a multiplier verilog code on xilinx ISE and I got the synthesis report and Post PAR static timing report as shown below.

What is actually these terms mean? How can I calculate the total delay of the circuit?

 

[TrickyDicky]

What exactly do you mean by "total delay"? the timing report indicates that if you provide a 200 MHz clock, it should all work without timing related problems.

 

[sharath666]

A timing report will list out all the timing paths in your design. It will also show whether that path is satisfying the timing requirements or not. Your job is to go through these paths and look at how you can convert failing paths to passing ones. "Total delay" is ambiguous..

 

[ads-ee]

Given the results of the timing reports you didn't give the tools any constraints at all.

Because of this you have a design that has inputs and outputs with large delays (in excess of the default clock period). You should add a constraint file with target clock frequency and input/output timing constraints.

 

[arishsu]

I need to calculate the time delay required to calculate the output after input is given. how can I calculate that?
And what is 'Maximum output required time after clock' mean?

 

[TrickyDicky]

What you need is nothing to do with the timing report. You need to calculate the latency, which is easily determined from the HDL - number of pipestages * clock period.

 

[arishsu]

What you need is nothing to do with the timing report. You need to calculate the latency, which is easily determined from the HDL - number of pipestages * clock period.

That means number of clock cycles*clock period? But in the report, the input arrival time before input(or the setup time) is more than clock period. Then how will it work?

 

[TrickyDicky]

But given what ADS-ee said, you dont appear to have set any constraints, so the timing report is fairly meaningless.

 

[arishsu]

How to set timing constraints and input/output constraints?

 

[ads-ee]

The following should help.

Here is the clock constraint:


and the input output constraint:
**broken link removed**