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What is the proper way to use same signals of an interface as input or output? I am aware that the way i am doing it, could end up with Xs since there are no restrictions in the use of the signals from the interface.
So what is the way to do this using the modports?
Code, Use signals as input...
Hi, I am using the switch from analoglib in Cadence. But, seems to behave wrongly, any suggestions on how to configure the switch to output the signal only when the control is activated?
Attached you can see my circuit and the results
Only when the control signal is activated the output should...
Hi, I am making a sense amplifier in Cadence but is not providing the right Vout. Every time I enable the sense amplifier does not change much, just outputting a voltage of 4.3V, which is very close to Vdd=5V. It suppose to output the difference of inputs multiplied by a gain (BL and NOT_BL)...
Usually that happens when you export a bunch of data in CVS in Cadence. This is a bug I guess that they need to fix. One way to verify this, is to identify which one is missing, and if you are able to export those individually with its correspondent CVS file, then is just not taking all the...
I am working in ADEXL and I have many graphs, I am able to save them as a CSV file by selecting all children curves but it is time consuming.
Could you help me to use a sequence of commands (code) to perform this without the graphic interface? The steps that I follow are attached in 5 images.
Probably you have solved this. So just in case, I edit my schematics with launching virtuoso, then click open, it should show your schematic if is detected by virtuoso. Otherwise, you can create a new schematic.
Thank you, indeed I need resistors. One more question, please suggest me code in cadence to build bigger ROMs instead of doing it by hand. I would like to build 1 GB ROM or bigger.
1605916027
Yes I added the resistors, is working now. Thanks. Could you please suggest me code in cadence to...
Hi, I am making some tests with a simple ROM memory built with CMOS transistors. But each the output remains all the time the same. The selection of a word line should activate the available transistors in this line and discharge Vdd through them. Any suggestions on how to make this happen in...
Hi, no is not from a text book. I did it my self and I following the principle of every time a word line is selected the Vdd will discharge through the transistor present in the word line, otherwise the Vdd will continue until the end, where the inverter will turn it into a logic zero. You can...
Hi. I am working out the reading data in a simple ROM, my question is, should I expect a don't care in "BIT LINE 1" when "WORD LINE 3" is active?
First, I show the basics about NMOS which are the transistors used in this diagram.
Then the small ROM diagram and tables that show the results when...
Hi, Attached you can find the netlist, which is a ring oscilator. The option settings for the transient analysis in ADEL Cadence. And the data generated when downloaded in .CSV file. Is important to say that this amount of data is required by cadence in order to run the simulation and if I...
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