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Re: ram or registers?
usually companies have latch or register arrays for small memory sizes (lets say up to 32x32)
those has for example 2+ times smaller area then flops (share some stuff, latches are smaller then flops)
has 1 read and 1 write port usually, or several version with different...
We are Verilog users and we end with SystemC-Verilog cosimulation.
This is true that (for Cadence tools for sure) there is no language-to-language overhead for SystemC-Verilog cosimulation, so whole DPI stuff is not advantage but problem (faster one then PLI, but still ...) for SystemVerilog...
RTL simulation is slow because:
- it emulates concurrency on sequential CPU
and there are less significant reasons like:
- Verilog or VHDL signals have several posible states and are much more complex then native CPU variables (need to be resolved, ...)
- if VCD file generation is enabled (in...
There are more diferences the similarities between ASIC and FPGA synthesis:
- target libraries have no similarities at all
- scan insertion has no sence in FPGA world; memory BIST has no sence to; any DFT has no sence because FPGA are premanufactured and tested already
- clock tree synthesis is...
Verification is task which never finnishes and could not be perfect.
You need to know that at very beginning, so you need to plan and prioratize features you want to check.
Vera or e could help to do more exostive testing, but only if you know what are you doing. Still it never could be perfect.
If you use Cadence nc_verilog + nc_systemc, there is almost no slow down when you do systemc-verilog cosimulation (actually depending on Verilog module compelxity, slow down exists, but only because Verilog implemenation is inherently slower then C++/SystemC implementation - I really beleive...
How to do system design?
SystemVerilog is not intendeed to be used for system-level modeling.
SystemC is language for you. You don't need any expensive tools in beggining (Some C++ debugger and waveform viewer are enough).
If you are talking about H.264 decoder:
- start with existing JM...
about verification
If we are talking about system level design, SW/HW co-design, co-verification, partitioning, Architecture level iteration: the only language usefull in this areas is SystemC.
For verification, I also strongly prefer SystemC over e, Vera, SystemVerilog or good old HDLs. It...
Combination of DRAM process with Standard Library Cell process adds several additional mask and is to costly - almost nobody do that.
Even if you still want to use DRAM embedded in your ASIC, you need to know that power consuption for DRAM is much bigger than for SRAM (not acceptable for batery...
Unfortunatelly, there are not to much time for learning in days full of time-to-market preasure. And new generations are coming each years, better equipped with knowledge for new abstraction level used in IC design, then us.
We could do 2 things:
- admit that we could not compete anymore, try...
Which types of memory you could use depends on memory compiler your company has (notice that memory compilers are extremelly expencive tools).
Still usage of 1-port memory is the best whenever it is possible, because small arbitration logic is much less costly that memory area increase (it is up...
You could download JM reference software, select options you want in encoder config file (probably you want to enable something that will match your further HW or HW/SW implementation), run encoder for various YUV streams and do profiling to see which amount of time is spent on which part of it...
Usually, in addition to used library cells, companies has some kind of macroes used for small memories (not bigger then 32x32, even for the smaller one Virage/Artisan/... memory could have smaller area). Common name is register arrays, latch arrays, etc.
If you don't have anything like this, you...
Initially, idea behind systemC was: 1 language for everything hardware, verification and software.
Today, it is clear that no company made synthesis tool with SystemC support.
Still , even without usage in hardware description, SystemC has big advantage over SystemVerilog in SW/HW co-design and...
Majority of verification environments used around are Verilog + C. Companies spend lot of time and efforts in developing of verification methodologies and they don't want to transit to anything, if they really don't need.
The only way to go to 'new' constraint-random verification philosophy is...
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