How to finish perfect verification?

[harryzhu]

I heard verification has 70% work according to the code writing and you'll have to write plenty of testbench code, but if you're do one large VLSI design, that'll be impossible to accomplish and ensure perfect. How to do it now?

I'm one fresh man and have no any experience to it. Can Vera or specman do it? What is the common method of this process?

Have a good day!

Best Regards,

 

[andromeda]

Verification is task which never finnishes and could not be perfect.
You need to know that at very beginning, so you need to plan and prioratize features you want to check.
Vera or e could help to do more exostive testing, but only if you know what are you doing. Still it never could be perfect.

 

[zhangpengyu]

Now I kow is Coverage driven verifcation.

 

[selingeorge]

Verification must cover all the stated requirements. Exception cases and other special test cases left out will be reported as bug in later stages and get corrected to improve the product. So the testbench should atleast have the test case for design requirement verification. Modularised approach is powerful for verificatin.

Best Regards,
George.

 

[amaccormack]

Its quite easy to get perfect verification. First get a Cold Fusion power generator, and attatch it to a perpetual motion machine. Then take a philosopher's stone and dip it in the fountain of youth. Then use a time-machine to meet Einstein and read his mind for some hints.

</heavy irony>

 

[Thomson]

I heard verification has 70% work according to the code writing and you'll have to write plenty of testbench code, but if you're do one large VLSI design, that'll be impossible to accomplish and ensure perfect. How to do it now?

Yes! the verification including the verification engineer and designer verfication efforst do reach such extent, and if you verify a quite large unit, you can perceive of this. Although currently, 100% coverage is an ad hoc topic in the EDA arena, and considerable methodologies such as executable specification have been proposed or have been adopted such as Coverage-driven, constraint-random, assertion-based; however this is still a very hard target to obtain. The causes are as follows: (1)the intent of the specification are not complete compared with the specification architect, since the interpretation of the spec is exercised by the designers and verification engineers, both responsible for the different stages of the system. (2) even the aforementioned progress is perfect, the spec is not perfect at all, which doesn't match all the requirements of the market. (3) the test scenarioes are enornous which cannot be fully exercised by the team, especially at the system-level.

I'm one fresh man and have no any experience to it. Can Vera or specman do it? What is the common method of this process?

Tools cannot help you solve all the verification problems, so first you shall set up the methodology and verification methods first, for example do you adopt the bottom-up or top-down methodology. Vera or specman just faciliate some coding or describing process not the result.

I recommend you shall read the book "write testbench" written by Janick Bergeron, you can search this e-book on this web!

 

[lcf0451]

If you have perfect verification, then there are no verification.

 

[AlexWan]

For different designs, TTM has different pressure. Verification only need ensure that the functionality between the design and specificaiton is equal.

So after you finished the code coverage and function coverage test, you may think that you have finish your verificaiton.
Certainly, the degree of your verification is relative with your percent of two coverages.