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Recent content by analogdesigncdac

  1. A

    pass Tx of LDO for VCO application

    Hai, Thanks for your reply. Its going to subthresold region (no triode region) at load currents(0--15mA),and above 15mA it comes into saturation region. my topology is first stage diffamp having diode connected looad followed by common soure amp and then followed with NMOS pass Tx in...
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    pass Tx of LDO for VCO application

    Hi Designing LDO for vco app. At LDO output cap is 2pF. NMOS is used as pass Tx. Load current steps from 0 to 30mA. Pass Tx coming to SAT region after load current reaches 15mA, before it is remaining in Subthresold region. Is it compulsory for NMOS Pass Tx to get saturation...
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    65nm 4mA CURRENT REFERENCE

    Hai I have to design a current reference of 4mA in 65nm technology(VDD=1.2v). In the circuit shown at the points A and B i need a voltage of 0.6v for my opamp biasing(MOS Vth 0.56v). with these combination of current and voltage the resistors i have to choose are below 1k. Is it ok to...
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    65nm CURRENT REFERENCE

    thanks for your reply
  5. A

    65nm CURRENT REFERENCE

    Hai In 65nm technology if we have to design current references(4mA, 10mA---) what type of circuit we have to choose either a simple betamultipler or a PTAT from a BANDGAP reference. Thank you satya
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    CMOS reference circuits for high frequency circuits

    Hai Thanks for your reply in the earlier post. I had one more query. In 65nm technology if we have to design current references(4mA to 10mA) what type of circuit we have to choose either a simple betamultipler or a PTAT from a BANDGAP reference. Thank you satya
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    CMOS reference circuits for high frequency circuits

    Hai What are the issues that we must take into consideration in designing reference circuits(voltage and current) for high frequency circuits thank you
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    VCO jitter measurement in transient analysis and pnoise analysis

    Hai, I am simulating active inductor VCO with free running frequency of 5GHz in 65nm technology. using transient analysis (enabled transient noise) the measurement of period jitter is 400ps In tran analysis the noise setttings, noiseseed 1, noisefmax 2.5G and...
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    laying out N+ poly resistor and other unsilicided and silicided poly resistors

    Hai, Thanks for your reply. I just want to make myself clear regarding the problem. Between unsilicided poly and silicided poly resistors we know the difference. But between simple N+ poly and unsilicided N+ poly what is the general difference. thanks satya
  10. A

    laying out N+ poly resistor and other unsilicided and silicided poly resistors

    laying out N+ poly resistor and unsilicided N+ poly resistors Hai I am using ST 65nm process. Its having the following poly resistors with different flavours N+, P+ poly resistor; unsilicided & silicided N and P ploy resistors. difference in laying out simple N+ poly and unsilicided...
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    DC sweep: plot from calculator STM 65nm designkit

    Hai Thanks for your reply. From ADE window i saved the required. I can't plot any of the operating point data (gm, VDSATM gds --- in DC sweep) from calculator. I tink i a clear satya - - - Updated - - - Hai Thanks for your reply. From ADE window i saved the required. I can't...
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    DC sweep: plot from calculator STM 65nm designkit

    Hai I am working on virtuoso 6.1.3, in ADE XL environment. I save operating points in DC sweep using save M0.m1:all And i am using wavescan. when i take the signal in calculator it looks like getdata("M1/m1:ids" ?result "dc-dc"). When i try to plot the signal from calculator i...
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    65nm STmicroelectronics design kit

    Hai, At present i am working in 65nm design kit from ST microelectronics. I load the model files using ARTIST kit window. In artist kit i don't find any option for including all the corners at a time for the simulation. I include different corners manually. If anybody aware of...
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    65nm small signal parameters of mos

    Hai erikl, sorted out the issue. Including SAVE MO.m1:all in saveop.scs file.gives the option to plot all small signal parameter in DC sweep. This solution i found in forums satya
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    65nm small signal parameters of mos

    Hai erikl, No, i didn't find in RB. I don't have any problem when i worked in 0.18u technology. There is a difference in the model file representation of both the technologies(0.18u & 65nm). In 65nm the parameters in the model file are represented in sub-circuit and we have all...
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