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hi every one
i am designing sar adc 26 Mhz and design input buffer as two stage ota with folded cascode as a core
i wanna make my buffer switchable which work in the sampling phase and be off the rest of the clock to save power
how can i make it ?
can i switch on vdd i.e connect vdd in...
hi all,
i have designed T.G switch with another dummy T.G for sampling switch , my clock is 20Mhz , i used it for sar adc 8-bit , so how can i measure snr and thd for this switch , how can i choose fin , Nrecord , Nwindow ??
please i am in deep need for answer :)
thx in advance :)
hi all,
kindly, i make sar adc 8-bit and i wanna measure its dynamic performance to calculate ENOB , my max i/p frequency is 574K and fs=2Mhz
i choose Nrecord=2048 and Nwindow=585 so fin=573.3K , is this true and what's exactly method to know i.p sinwave needed in fft?
thx in advance
i design sar adc and there is a proplem in sar logic code
the command @(initial_step) saw the first command only (ex. see counter=0) and the other statement repeated in code and i want to make them initial only
this is the code
// VerilogA for try, try, veriloga
`include "constants.vams"...
hi all,
how can i know the value of reference voltage of ADC and what's its effect ?
also how to determine the value of unit capacitor in DAC in SAR ADC ?
hi , how r u all guys ?
i am in my 4th year of electronics and in my graduation project i will make low power ADC , so i want your advice to me how to start? first i want to know about system of adc in general , so where can i start from and from what source?
another question , when i start to...
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