amr hema
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hi every one
i am designing sar adc 26 Mhz and design input buffer as two stage ota with folded cascode as a core
i wanna make my buffer switchable which work in the sampling phase and be off the rest of the clock to save power
how can i make it ?
can i switch on vdd i.e connect vdd in sampling and disconnect in the rest clock
thx in advance
i am designing sar adc 26 Mhz and design input buffer as two stage ota with folded cascode as a core
i wanna make my buffer switchable which work in the sampling phase and be off the rest of the clock to save power
how can i make it ?
can i switch on vdd i.e connect vdd in sampling and disconnect in the rest clock
thx in advance
