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Recent content by altair_06

  1. A

    I2C receiving/transmitting system design

    Hi, I am not clear about your question. Do u want to design a I2C Master or Slave?
  2. A

    Question about the behaviour of an I2C which is acting as a master

    Hi, I have a doubt regrading the behaviour of an I2C which is acting as a master. Suppose an I2C Master with an APB interface has a slave address written which is not present, what would be the behaviour of the Master. Does it transmit the slave address once and on not seeing the ack will...
  3. A

    Help me modify divide by 2 counter code to divide by 4 counter

    divide by four counter Hi, Use a counter to count two clock cycles and then invert the output. Hope u got an idea.
  4. A

    How to generate a 48 MHz clock

    Hi, It is for simulation purpose only. This 48 MHz clock is used as a reference clock by a module to generate various different baud clocks.
  5. A

    How to generate a 48 MHz clock

    Hi, I want to generate exact 48 MHz clock. Currently i tried to generate by using delays of 20.84, but i am able to generate 47.98 MHz. Hence i thought of deriving it from a higher frequency clock. I am also not sure what higher frequency to select to derive exact 48 MHz clock.Hope u...
  6. A

    How to generate a 48 MHz clock

    Hi, I am writing a verilog code and i need to generate a 48 MHz clock using any reference clock. Can u give me any suggestions?
  7. A

    How to generate a 48 MHz clock

    Hi, How to generate a 48 MHz clock from a 100 MHz clock?
  8. A

    clarification on I2C scl clock

    Hi friends, I need a clarification on I2C scl clock. When I2C device acts as slave will it need any internal refference clock or input scl clock alone is sufficient to sample the data ? 1.since I2C master has the capability of controlling the scl line (pull up the scl line) 2.onother...
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    Questions about clock signals in I2C slave clock

    Hi friends, I need a clarification on I2C scl clock. When I2C device acts as slave will it need any internal refference clock or input scl clock alone is sufficient to sample the data ? 1.since I2C master has the capability of controlling the scl line (pull up the scl line) 2.onother...
  10. A

    How to pass values to inout arguments in Verilog?

    Hi , If i have inout arguments in a task, how do i pass values to them. can anyone suggest me a solution regards altair
  11. A

    Need info about Verilog

    Hi, I would prefer Verilog by Samir Palnitkar. U can get many tutorials as well as books on verilog in this forum. U can search for that.I have posted one of the links found which would be useful. thanks altair
  12. A

    How to implement SHA 256 in Verilog or C?

    Re: SHA 256 Hi.. I have done an implementation in verilog of SHA -256. If u have any queries regarding that u can mail it to me or post it here.
  13. A

    Help me out clearing this timing violation

    Hi ... Can anyone help me out in clearing this timing violation. These are the violations i get when i run timing simulation. Warning! Timing violation $setuphold<setup>( posedge CLK:4758 PS, posedge CE &&& (ce_clk_enable != 0):4394 PS, 510 : 510 PS, -58 : -58 PS )...
  14. A

    files needed for timing simulation

    HI , For Timing simulation, do i need both SIMPRIMS and UNISIMS library or only SIMPRIMS is enough.
  15. A

    files needed for timing simulation

    HI ... can anyone tell me the files required for doing a timing simulation. I have obtained a netlist(.v) and a .sdf file from xilinx8.2 ise. I need to do timing simulation using NC Verilog. Where can i find the libraries in the linux environment.
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