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Recent content by ajhunt18

  1. A

    report_delay_calculation problem with 2-input nand gate

    Okay. Thanks! But should I add the cell delays given by the 2 RDC reports?
  2. A

    report_delay_calculation problem with 2-input nand gate

    What will be the command if I am to calculate the delay of a 2-input nand gate? what should I put in the "-from" portion? please help.
  3. A

    [SOLVED] report_delay_calculation problem

    Okay, thank you. I'll do that. By the way, what will be the command if I am to calculate the delay of a 2-input nand gate? what should I put in the "-from" portion? :???:
  4. A

    [SOLVED] report_delay_calculation problem

    I have discovered this report_delay_calculation command in Design Compiler (DC), but having problems implementing it. I have attached a screenshot of the error report in DC. Anyone, please help. Thank you!
  5. A

    inout port+testbench problem, verilog

    Re: verilog driving inout atena's right, you should break your design into submodules. For example, in module 1, you can set SDA as input and in module 2, set SDA as output. Then finally, in your top module, set SDA as a wire. No need to define SDA as an inout port. I have had this problem...
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    How to implement inout port or feedback in DCO (in verilog HDL)? Dead output in VCS.

    Below is my verilog code for DCO. I am not sure if the problem is with the inout port (dco_out). Because the output in VCS is always dead :-|. I already made a testbench for this: `timescale 1ps/1ps module dco (enable, coarse_ctrl_code, fine_ctrl_code, fine_mux_out, dco_out); input enable...
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    Looking for synthesizable VHDL /Verilog code for a simple adpll

    Re: code for adpll Hi, do you still have a copy of the verilog code from the website "http://www-unix.ecs.umass.edu"? or do you have a working verilog code for adpll? i am having troubles with mine. :/
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    error (PSYN-117) in icc_shell, please help.

    I've used that solution earlier but it seems the command "find" has been disabled. It means that it is obsolete (from this link: https://book.huihoo.com/pdf/crafting-a-chip-a-practical-guide-to-the-uofu-vlsi-cad-flow/handouts/dcxg.pdf). ) and must be removed. Also, the "is_pad.tcl" command is...
  9. A

    error (PSYN-117) in icc_shell, please help.

    Can anyone please help me? The error log PSYN - 117 can be seen in the attached image. Any help will be very much appreciated. Thanks! btw, i am designing a Digitally-Controlled Oscillator or DCO.
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    is it possible to write a verilog code for DCO?

    do you know how to write a code for a DCO in verilog? pls help. thanks!
  11. A

    set_dont_touch command in DC, need help asap

    yeah, thanks a lot! :)
  12. A

    set_dont_touch command in DC, need help asap

    How to use this command? I tried using this command but nothing happens. It was not supposed to optimize my design, but still DC optimized it. What should be the correct method or steps in using this command in DC? Was it after I compile the design? or Before compiling the design? or before...
  13. A

    What is DCO Control/Controller?

    I am designing a Digitally Controlled Oscillator for an ADPLL Design. I have come across with the term DCO Control. What is a DCO Control? Is it an external block or another block of a PLL? It's because I need to measure/know the DCO Control Word Length and I don't have an idea what a DCO...
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    How to measure the resolution of a DCO in synopsis?

    I am designing a DCO using Verilog. How can we measure the resolution of the DCO? I think it's in ps
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    Can we design a DCO using verilog? Is it synthesizable?

    I am not sure but yes, it is an NCO. Is DCO too general? I am planning to design it for PLL. I haven't read about NCO yet.
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