How to implement inout port or feedback in DCO (in verilog HDL)? Dead output in VCS.

[ajhunt18]

Below is my verilog code for DCO. I am not sure if the problem is with the inout port (dco_out). Because the output in VCS is always dead :-|. I already made a testbench for this:



`timescale 1ps/1ps


module dco (enable, coarse_ctrl_code, fine_ctrl_code, fine_mux_out, dco_out);

input enable;
input [3:0] coarse_ctrl_code;

inout dco_out;
output fine_mux_out;

wire oe; // add this control signal
wire signal_input;
reg reg_out;

assign dco_out = oe ? reg_out : 1'bz;
assign signal_input = dco_out;


reg mux_out;

wire nand_out;
wire [15:0] Or;

//coarsedecoder_always output pin

wire [15:0] coarsedecoder_out;

//finedecoder_always and fine input/output pins
input fine_ctrl_code;
reg finedecoder_out;
wire [1:0] fine_out;
wire fine_mux_out;


buf buffer1(fine_mux_out, dco_out);


assign nand_out = ~(enable & dco_out);

assign #680 Or[0] = ~(nand_out & coarsedecoder_out[0]);
assign #740 Or[1] = ~(Or[0] & coarsedecoder_out[1]);
assign #800 Or[2] = ~(Or[1] & coarsedecoder_out[2]);
assign #860 Or[3] = ~(Or[2] & coarsedecoder_out[3]);
assign #920 Or[4] = ~(Or[3] & coarsedecoder_out[4]);
assign #970 Or[5] = ~(Or[4] & coarsedecoder_out[5]);
assign #1030 Or[6] = ~(Or[5] & coarsedecoder_out[6]);
assign #1080 Or[7] = ~(Or[6] & coarsedecoder_out[7]);
assign #1140 Or[8] = ~(Or[7] & coarsedecoder_out[8]);
assign #1190 Or[9] = ~(Or[8] & coarsedecoder_out[9]);
assign #1260 Or[10] = ~(Or[9] & coarsedecoder_out[10]);
assign #1320 Or[11] = ~(Or[10] & coarsedecoder_out[11]);
assign #1380 Or[12] = ~(Or[11] & coarsedecoder_out[12]);
assign #1440 Or[13] = ~(Or[12] & coarsedecoder_out[13]);
assign #1500 Or[14] = ~(Or[13] & coarsedecoder_out[14]);
assign #1550 Or[15] = ~(Or[14] & coarsedecoder_out[15]);


always @ (Or or coarse_ctrl_code)
if (coarse_ctrl_code == 4'b0000)
mux_out = Or[0];
else
if (coarse_ctrl_code == 4'b0001)
mux_out = Or[1];
else
if (coarse_ctrl_code == 4'b0010)
mux_out = Or[2];
else
if (coarse_ctrl_code == 4'b0011)
mux_out = Or[3];
else
if (coarse_ctrl_code == 4'b0100)
mux_out = Or[4];
else
if (coarse_ctrl_code == 4'b0101)
mux_out = Or[5];
else
if (coarse_ctrl_code == 4'b0110)
mux_out = Or[6];
else
if (coarse_ctrl_code == 4'b0111)
mux_out = Or[7];
else
if (coarse_ctrl_code == 4'b1000)
mux_out = Or[8];
else
if (coarse_ctrl_code == 4'b1001)
mux_out = Or[9];
else
if (coarse_ctrl_code == 4'b1010)
mux_out = Or[10];
else
if (coarse_ctrl_code == 4'b1011)
mux_out = Or[11];
else
if (coarse_ctrl_code == 4'b1100)
mux_out = Or[12];

else
if (coarse_ctrl_code == 4'b1101)
mux_out = Or[13];
else
if (coarse_ctrl_code == 4'b1110)
mux_out = Or[14];
else
mux_out = Or[15];



//coarsedecoder_always


assign coarsedecoder_out = (coarse_ctrl_code == 4'b0000) ? 16'b0000000000000001:
(coarse_ctrl_code == 4'b0001) ? 16'b0000000000000011:
(coarse_ctrl_code == 4'b0010) ? 16'b0000000000000111:
(coarse_ctrl_code == 4'b0011) ? 16'b0000000000001111:
(coarse_ctrl_code == 4'b0100) ? 16'b0000000000011111:
(coarse_ctrl_code == 4'b0101) ? 16'b0000000000111111:
(coarse_ctrl_code == 4'b0110) ? 16'b0000000001111111:
(coarse_ctrl_code == 4'b0111) ? 16'b0000000011111111:
(coarse_ctrl_code == 4'b1000) ? 16'b0000000111111111:
(coarse_ctrl_code == 4'b1001) ? 16'b0000001111111111:
(coarse_ctrl_code == 4'b1010) ? 16'b0000011111111111:
(coarse_ctrl_code == 4'b1011) ? 16'b0000111111111111:
(coarse_ctrl_code == 4'b1100) ? 16'b0001111111111111:
(coarse_ctrl_code == 4'b1101) ? 16'b0011111111111111:
(coarse_ctrl_code == 4'b1110) ? 16'b0111111111111111:
(coarse_ctrl_code == 4'b1111) ? 16'b1111111111111111: 16'h00;




//fine

not fine1(fine_out[0], mux_out);
assign fine_mux_out = (fine_ctrl_code == 1'b0) ? mux_out:fine_out[0];



endmodule



Here's my testbench:



`timescale 1ps/1ps

module top;

reg enable;
reg [3:0] coarse_ctrl_code;
reg fine_ctrl_code;
wire dco_out;


dco uut (
.enable(enable),
.coarse_ctrl_code(coarse_ctrl_code),
.fine_ctrl_code(fine_ctrl_code),
.dco_out(dco_out)
);

initial begin
enable = 0;

#4000 enable = 1;

coarse_ctrl_code = 4'b0001;
fine_ctrl_code = 1'b0;


end

endmodule




Any help would be much appreciated. Thanks!

 

[FvM]

oe is undriven. There may be more errors.

P.S.: reg_out is also undriven. I gave up to understand the design operation after looking into it's details.