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Does any one know of any circuit techniques to reduce the history effect in floating body transistors ? I have a circuit which is showing a lot of history depending on the input pattern.
Does anyone Know of any helpful papers? I would like to stick with the floating body transistors as it...
cml to cmos converter
Can anyone point me to various topologies for a CML-to-CMOS converter?
I am looking for topoloies with lower powerconsumption across corners than what i am using.
pointers to any free literature would be great too
cml flip flop
I am trying to design a DFF with extremely small aperture. What is the best way to achieve this? In the flop, I am using the conventional latch architecture with resistive loads.
Is there a better way to do this?
Do you have any literature on improving arpeture time?
Does any one have any information/experience on whether it is best to keep the CML latches ( Master/Slave latch )in a D-flipflop design the same size?
I need as small an arpeture as I can get...
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